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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74191 )
Change subject: mb/amd/mayan: Update DXIO descriptors per schematics
......................................................................
Patch Set 3:
(5 comments)
File src/mainboard/amd/mayan/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74191/comment/e1fb9c0b_bc59700c
PS3, Line 42: .link_aspm = 2,
Prefer using the enums in vc/amd/fsp/phoenix/platform_descriptors.h - `ASPM_L1` here
This also applies to the other entries
https://review.coreboot.org/c/coreboot/+/74191/comment/13661fe5_def3ee2c
PS3, Line 43: .link_aspm_L1_1 = 1,
: .link_aspm_L1_2 = 1,
Prefer using `true` here over `1`
https://review.coreboot.org/c/coreboot/+/74191/comment/d8be3362_40c511e5
PS3, Line 47: .clk_pm_support = 1,
Does the FSP support this?
https://review.coreboot.org/c/coreboot/+/74191/comment/90fc1683_d54bd3d8
PS3, Line 66: //.gpio_group_id = 30,
Is this just a placeholder for now? If so, please add "TODO". If not, please remove
https://review.coreboot.org/c/coreboot/+/74191/comment/97998a2c_70b65ddf
PS3, Line 90: },
GBE? SD card? WLAN?
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Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/stoneyridge/acpi.c:
https://review.coreboot.org/c/coreboot/+/74430/comment/061d9504_649c0744
PS2, Line 78: fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
> Felix, do you think this would require a CPU _PTC to work? After Processor() was dropped P_BLK/P_CNT […]
CB:74473 in case you need it.
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Change subject: mb/google/rex: Initial setup for gpio config
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Set Ready For Review
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Change subject: mb/google/rex: Initial setup for ramstage/early gpio config
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74475/comment/5894a75b_545e0ac2
PS1, Line 9: This adds the initial gpio configuration for the screebo initial variant.
> Possible unwrapped commit description (prefer a maximum 72 chars per line)
Please fix.
File src/mainboard/google/rex/variants/screebo/gpio.c:
https://review.coreboot.org/c/coreboot/+/74475/comment/77f18806_b19c164d
PS1, Line 39: PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
> please, no spaces at the start of a line
Please fix.
https://review.coreboot.org/c/coreboot/+/74475/comment/4f1ed431_1ab4315b
PS1, Line 65: PAD_CFG_NF_LOCK(GPP_B11, NONE, NF1, LOCK_CONFIG),
> trailing whitespace
Please fix.
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Change subject: mb/google/rex: Initial setup for ramstage/early/romstage gpio config for screebo
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Patch Set 1:
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Change subject: mb/google/rex: Initial setup for ramstage/early/romstage gpio config for screebo
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174275):
https://review.coreboot.org/c/coreboot/+/74475/comment/cf538bce_670b1f7f
PS1, Line 9: This adds the initial gpio configuration for the screebo initial variant.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
File src/mainboard/google/rex/variants/screebo/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174275):
https://review.coreboot.org/c/coreboot/+/74475/comment/0601f156_cdbc1965
PS1, Line 39: PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174275):
https://review.coreboot.org/c/coreboot/+/74475/comment/49e1b8af_2ac8bf7e
PS1, Line 65: PAD_CFG_NF_LOCK(GPP_B11, NONE, NF1, LOCK_CONFIG),
trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174275):
https://review.coreboot.org/c/coreboot/+/74475/comment/d9d0c733_3253256a
PS1, Line 89: PAD_NC(GPP_B23, NONE),
please, no spaces at the start of a line
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