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Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
......................................................................
Patch Set 18:
(6 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/66545/comment/bd43954e_b851fffc
PS16, Line 7: mainboard
> mb
Done
https://review.coreboot.org/c/coreboot/+/66545/comment/84b388f0_e143ea88
PS16, Line 10: Boot Seabios -> Linux
> Please add the versions (also below).
Done
https://review.coreboot.org/c/coreboot/+/66545/comment/e93adcd7_ac6cc134
PS16, Line 10: Seabios
> SeaBIOS
Done
https://review.coreboot.org/c/coreboot/+/66545/comment/ab3c452f_c8f10391
PS16, Line 10: Boot Seabios -> Linux
: Boot EDK2 -> Linux, Windows 10
: M.2 SSD Slot 1: PCH SSD
: M.2 SSD Slot 2: PCH SSD
: M.2 SSD Slot 3: PCH SSD, Backside
: SATA Cable Port 1-3
: SATA Direct Connect Port
: DisplayPort Port 1,2
: HDMI Port 1,2
: PCIE x4 Slot 1
: PCIE x4 Slot 3
: USB Ports 1-4 (Backpanel)
: M.2. CNVI: WiFi (Linux works, Win 10 does not)
: S3 (suspend to ram) (Linux works, Win 10 does not)
> Would be nice if you formatted it as a list.
Done
File src/mainboard/intel/adlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/66545/comment/0ac623fd_7c2e5ca1
PS17, Line 17: select SOC_INTEL_COMMON_BLOCK_IPU
> How about: […]
Done
File src/mainboard/intel/adlrvp/ramstage.c:
https://review.coreboot.org/c/coreboot/+/66545/comment/4df3e745_38241a0f
PS17, Line 67: //TODO find out if it's an ADL-S thing or board specific
> Alternatively, move the Type-C stuff to a separate compilation unit and do not include it for ADL-S
I just wrapped it around preprocessor (I am too lazy). Hope that's also ok.
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Change subject: mb/starlabs/starbook: Add ramtop_cmos_offset
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Was this tested with/without USE_OPTION_TABLE enabled?
File src/mainboard/starlabs/starbook/cmos.layout:
https://review.coreboot.org/c/coreboot/+/74432/comment/796b5b89_ff3fde08
PS2, Line 42: 800
The ramstop feature doesn't seem to use the option table API and I don't see
anything that would update the option table checksum. So, should this be outside
the checksum region?
(I also don't understand why it's stored at a hardcoded location even with
USE_OPTION_TABLE enabled.)
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Change subject: asus/p2b: Remove MADT LAPIC
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Tested on the asus p2-99.
It seems to have fixed the issue.
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Change subject: include/cpu/x86/lapic.h: Add constraint for SMM
......................................................................
Patch Set 2:
(1 comment)
File src/include/cpu/x86/lapic.h:
https://review.coreboot.org/c/coreboot/+/74054/comment/cbc8adea_46cec172
PS2, Line 64: is_x2apic_mode
The whole function is wrong. It assumes that state of the apic, but that's not valid until MPinit has run.
When CONFIG_X2APIC_ONLY is selected and something is calling lapicid() before MPinit it'll cause an exception. As the exception handler also calls lapicid() it tripple faults.
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Change subject: aopen/dxplplusu: Drop ACPI C-states support
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Patch Set 2: Code-Review+1
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Change subject: mb/google/rex: Initial setup for gpio config
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74475/comment/b0421dc7_7726b126
PS3, Line 2: liukun11
Please configure your user name.
$ git config --global user.name "…"
$ git commit --amend --author="… <…>"
https://review.coreboot.org/c/coreboot/+/74475/comment/e04948e3_3a6d7ff4
PS3, Line 7: mb/google/rex: Initial setup for gpio config
Please make it a statement, by adding a verb (in imperative mood); cf `git log --oneline`.
https://review.coreboot.org/c/coreboot/+/74475/comment/261072d0_7224bbe6
PS3, Line 9: add the initial gpio configuration for the screebo
What is the source for this?
https://review.coreboot.org/c/coreboot/+/74475/comment/7961884f_b88987dd
PS3, Line 14: liukun11
Ditto.
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