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Hello build bot (Jenkins), Werner Zeh, Jan Samek,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74650
to look at the new patch set (#4).
Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
......................................................................
mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).
Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74650/4
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Attention is currently required from: Mario Scheithauer, Werner Zeh.
Hello build bot (Jenkins), Werner Zeh, Jan Samek,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74628
to look at the new patch set (#4).
Change subject: mb/siemens/mc_ehl4: Adjust GPIOs
......................................................................
mb/siemens/mc_ehl4: Adjust GPIOs
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must
be adjust according to the circuit diagram for this mainboard.
Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/gpio.c
1 file changed, 20 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/74628/4
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74716 )
Change subject: soc/amd/common/block: Add missing cbfs_unmap().
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74716/comment/20dc4cee_efb1cf6d
PS1, Line 16: Change-Id: Ibbebe7401e9f5a5312da1216408bf42fa2449db1
Please fix: `No Signed-off-by line in commit message`
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/74716/comment/486c85bd_c0043c1f
PS1, Line 113: if (cpus_updated == get_cpu_count())
paranoid-nit: `>=`
File src/soc/amd/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/74716/comment/623a5431_7912517a
PS1, Line 173: cbfs_unmap(rom);
There are scenarios where this call will be incorrect. `pci_rom_probe(dev)` does not guarantee the returned pointer to be a CBFS file. Right now `cbfs_unmap(ptr)` unmaps only pointers it had allocated but it's not guaranteed. Please see, if you can solve this some other way.
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Change subject: soc/intel/common: Fix long delay when ME is disabled
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/74435/comment/eccfc9e7_d7768577
PS1, Line 273: AND
Please update the API description to reflect the current "if condition" change.
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Change subject: acpi: Add missing cbfs_unmap()
......................................................................
Patch Set 1:
(2 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/74715/comment/ab49046b_ff49e191
PS1, Line 1860: slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size);
I think SLIC also should get unmapped.
https://review.coreboot.org/c/coreboot/+/74715/comment/008e40fb_028726d9
PS1, Line 1951: acpi_add_table(rsdp, slic);
+ `cbfs_unmap(slic_file);`
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Change subject: util: Use common ARRAY_SIZE define
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@Robert, @Felix, @Christian, I'd be grateful for the review.
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Change subject: soc/amd/common/block: Add missing cbfs_unmap().
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174836):
https://review.coreboot.org/c/coreboot/+/74716/comment/b0f06091_a481baed
PS1, Line 6:
Subject line should not end with a period.
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Change subject: mb/siemens/mc_ehl4: Adjust GPIOs
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> I am not sure about this, Jan. […]
OK, understand.
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