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Change subject: mb/siemens/mc_ehl4: Adjust GPIOs
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
> I might suggest mentioning also the GPIOs that have a default value or are NC. […]
I am not sure about this, Jan. If we want to have _all_ GPIOs mentioned in the tables then the tables will become quite long due to the vast amount of configurable GPIOS. This in turn will decrease readability a lot, IMHO.
In addition, there are GPIOs that are set up by FSP and the configuration is done via devicetree. So there is no real, useable way in having all GPIOs described in in a single place anyway.
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Change subject: mb/google/skyrim: Add mainboard chip.h
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS5:
> it's still describing the hardware, it's just describing it in the context of the board. It's providing additional descriptive information about the hardware.
Adding a chip that does not exist and has no operations is not the way to go. I suggest adding functionality to include a mainboard header in sconfig.
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Change subject: mb/siemens/mc_ehl4: Disable PCIe device I2C4
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> The reason I2C4 was left enabled is that it is function 0 of this device. […]
You are right. I will abandon this change.
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Change subject: soc/intel/common: Fix long delay when ME is disabled
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74435/comment/8f9ea49f_91021d50
PS1, Line 14:
: This is because the current code only checks if the ME is
: disabled for CSE LITE SKUs. With this patch, boot times are
: approximately 5 seconds quicker:
> " […]
so i guess it makes sense for this patch to adapt the same flow as chrome os with cse_is_hfs1_com_soft_temp_disable?
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Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/siemens/mc_ehl4: Adjust USB settings
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Patch Set 3: Code-Review+2
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Change subject: mb/siemens/mc_ehl4: Switch RTC type and connection
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Patch Set 3: Code-Review+2
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Change subject: soc/amd/mendocino: Print content of manifest file
......................................................................
Patch Set 4:
(2 comments)
File src/soc/amd/mendocino/manifest.c:
https://review.coreboot.org/c/coreboot/+/74269/comment/10c8ada2_2a9e54a8
PS3, Line 12: {
> Nit: Open brace not required for single statement if block.
Done
https://review.coreboot.org/c/coreboot/+/74269/comment/d8b9bdda_ba3dccb1
PS3, Line 16: Blobs
> Nit: AMDFW Blobs version
Done
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Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
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Change subject: mb/siemens/mc_ehl4: Disable PCIe device I2C4
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Patchset:
PS3:
The reason I2C4 was left enabled is that it is function 0 of this device. Now that you disable it the UART function will become 19.0 which might be confusing. Please do not disable function 0.
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