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Change subject: soc/amd/common/psp_verstage: Map/unmap boot device on need basis
......................................................................
Patch Set 1:
(3 comments)
File src/soc/amd/common/psp_verstage/boot_dev.c:
https://review.coreboot.org/c/coreboot/+/74606/comment/673b683e_520045b3
PS1, Line 22: svc_map_spi_rom
Will this set mapping to NULL on failure?
https://review.coreboot.org/c/coreboot/+/74606/comment/263c1f1f_11a2db88
PS1, Line 22: size
Does this have any alignment restrictions?
File src/soc/amd/common/psp_verstage/fch.c:
https://review.coreboot.org/c/coreboot/+/74606/comment/30935194_740276b1
PS1, Line 100: SpiBiosSmnBase
Is this really a `void *`?
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Change subject: mb/google/skyrim: Add mainboard chip.h
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74609/comment/ddb33b4f_5d36bf59
PS8, Line 2: chip mainboard/google/skyrim/variants/baseboard
Hrmm, I agree with Arthur, this looks strange. The goal is to just include a mainboard specific `.h` in the `static.c`. We can either make the device tree parser look for a mainboard/devicetree.h, or we can include a mainboard specific header in the soc/amd/mendocino/chip.h. The former is probably the least surprising.
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Change subject: mb/google/skyrim/var/markarth: Change to read the eMMC clkreq instead
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/skyrim/variants/markarth/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74583/comment/3ab3106f_71e78578
PS4, Line 77: 115
Just a note: This change is functionally right. But in the future instead of number, I would prefer to use GPIO_115 as defined in soc/gpio.h. Jon is working on fixing it for Skyrim program - atleast fixable for port_descriptors.c. So no further effort required.
We learnt that in older SoCs, GPIO_NNN != NNN.
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Change subject: soc/amd/common/block: Add missing cbfs_unmap().
......................................................................
Patch Set 1:
(2 comments)
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/74716/comment/c47bfc18_1be89108
PS1, Line 83: struct microcode *ucode = NULL;
This variable is only valid inside the `if` block below.
https://review.coreboot.org/c/coreboot/+/74716/comment/6a003d30_bfdb9663
PS1, Line 114: ucode
cache_valid should be false now.
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Change subject: mb/amd/mayan: Update DXIO descriptors per schematics
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74191/comment/c1ac9d08_52b612b0
PS2, Line 7: for mayan
> This was lost in the latest patch set
good catch, thanks. I have fixed it.
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Hello build bot (Jenkins), Jason Glenesk, ritul guru, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74191
to look at the new patch set (#5).
Change subject: mb/amd/mayan: Update DXIO descriptors per schematics
......................................................................
mb/amd/mayan: Update DXIO descriptors per schematics
Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e
Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com>
---
M src/mainboard/amd/mayan/port_descriptors.c
1 file changed, 81 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/74191/5
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Change subject: drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)
......................................................................
Patch Set 12:
(6 comments)
File src/drivers/i2c/pi608gp/pi608gp.h:
https://review.coreboot.org/c/coreboot/+/74433/comment/a565ad91_2ab97501
PS12, Line 10: #define DEEMPH_LVL_MV(_LVL, _LVL_10) {.lvl = _LVL, .lvl_10 = _LVL_10}
Add spaces after { and before }?
File src/drivers/i2c/pi608gp/pi608gp.c:
https://review.coreboot.org/c/coreboot/+/74433/comment/3ec4b4bf_58b7666d
PS12, Line 17: /* Only some of the available registers are implemented.
: For a full list, see the PI7C9X2G608GP datasheet. */
As it’s not in a function body you could use:
/*
* […]
*/
https://review.coreboot.org/c/coreboot/+/74433/comment/ecf9b76a_be4fa8a3
PS12, Line 26: level
Add the unit to the name?
https://review.coreboot.org/c/coreboot/+/74433/comment/b53cd293_d155f7f1
PS12, Line 48: { 0, 0}
Use spaces consistently?
https://review.coreboot.org/c/coreboot/+/74433/comment/8aaad4fb_87d21b6a
PS12, Line 54: uint8_t
Please use int [1]?
[1]: https://notabs.org/coding/smallIntsBigPenalty.htmhttps://review.coreboot.org/c/coreboot/+/74433/comment/cc4c6ebe_e74c8e1f
PS12, Line 71: /* Compose the SMBus message for register read init operation (from MSB to LSB):
: Byte 1: 7:3 = Rsvd., 2:0 = Command,
: Byte 2: 7:4 = Rsvd., 3:0 = Port Select[4:1],
: Byte 3: 7 = Port Select[0], 6 = Rsvd., 5:2 = Byte Enable, 1:0 = Reg. Addr. [11:10],
: Byte 4: 7:0 = Reg. Addr.[9:2] (Reg. Addr. [1:0] fixed to 0). */
Maybe use non-concise form?
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Change subject: Revert "util/ifdtool: Add option to create FMAP template"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74692/comment/e44b60ca_665a0dfb
PS2, Line 11: Above commit inserts multiple IFD regions not present into the default
: FMAP template, some of which overlap, resulting in far less space
: available for BIOS region / CBFS.
> Did you have issues with an IFD on a board? Was the IFD faulty somehow?
I'm having issues building all of the google/glados variants (Skylake). This is what the generated fmap.fmd ends up being:
FLASH@4278190080 0x01000000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x1FF000
SI_IE@0x7FFF000 0x1000
SI_10GBE0@0x7FFF000 0x1000
SI_10GBE1@0x7FFF000 0x1000
(null)@0x7FFF000 0x1000
(null)@0x7FFF000 0x1000
SI_PTT@0x7FFF000 0x1000
SI_BIOS@12255232 4521984 {
RW_MRC_CACHE@0 0x10000
SMMSTORE@65536 0x40000
RO_VPD@327680 0x4000
FMAP@344064 0x200
COREBOOT(CBFS)@344576 4177408
}
}
the error I get building is:
FMAP build/util/cbfstool/fmaptool -h build/fmap_config.h build/fmap.fmd build/fmap.fmap
syntax error
FATAL: Failed while processing provided descriptor
it seems possible this is an issue with ifdtool, since using the `-p sklkbl` flag produces a layout with those bogus fields. Running ifdtool without `-p` shows the correct layout:
without -p:
Found Region Section
FLREG0: 0x00000000
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1: 0x0fff0200
Flash Region 1 (BIOS): 00200000 - 00ffffff
FLREG2: 0x01ff0001
Flash Region 2 (Intel ME): 00001000 - 001fffff
FLREG3: 0x00007fff
Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
FLREG4: 0x00007fff
Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
with -p sklkbl (which is what the build system is doing):
Found Region Section
FLREG0: 0x00000000
Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
FLREG1: 0x0fff0200
Flash Region 1 (BIOS): 00200000 - 00ffffff
FLREG2: 0x01ff0001
Flash Region 2 (Intel ME): 00001000 - 001fffff
FLREG3: 0x00007fff
Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
FLREG4: 0x00007fff
Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
FLREG5: 0x00007fff
Flash Region 5 (Device Exp1): 07fff000 - 00000fff (unused)
FLREG6: 0x00007fff
Flash Region 6 (Secondary BIOS): 07fff000 - 00000fff (unused)
FLREG8: 0x00007fff
Flash Region 8 (EC): 07fff000 - 00000fff (unused)
FLREG9: 0x00007fff
Flash Region 9 (Device Exp2): 07fff000 - 00000fff (unused)
FLREG10: 0xffffffff
Flash Region 10 (IE): 07fff000 - 07ffffff
FLREG11: 0xffffffff
Flash Region 11 (10GbE_0): 07fff000 - 07ffffff
FLREG12: 0xffffffff
Flash Region 12 (10GbE_1): 07fff000 - 07ffffff
FLREG13: 0xffffffff
Flash Region 13 (Reserved): 07fff000 - 07ffffff
FLREG14: 0xffffffff
Flash Region 14 (Reserved): 07fff000 - 07ffffff
FLREG15: 0xffffffff
Flash Region 15 (PTT): 07fff000 - 07ffffff
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Change subject: asus/p2b: Remove MADT LAPIC
......................................................................
Patch Set 5:
(1 comment)
File src/southbridge/intel/i82371eb/Kconfig:
https://review.coreboot.org/c/coreboot/+/74472/comment/0e9ba713_66574346
PS4, Line 2: select ACPI_COMMON_MADT_LAPIC
> hadn't looked a those yet
oh, i already reviewed the first of those two
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