coreboot-gerrit October 2023

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[M] Change in coreboot[main]: soc/amd/genoa: Enable uart
by Varshit Pandya (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Arthur Heymans, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76507?usp=email ) Change subject: soc/amd/genoa: Enable uart ...................................................................... soc/amd/genoa: Enable uart Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc M src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/uart.h A src/soc/amd/genoa/uart.c 5 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/76507/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Gerrit-Change-Number: 76507 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/amd/genoa: Add GPIO support
by Varshit Pandya (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Martin Roth, Varshit Pandya. Hello Martin Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78222?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Martin Roth, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/amd/genoa: Add GPIO support ...................................................................... soc/amd/genoa: Add GPIO support Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig M src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/gpio.c 3 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/78222/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78222?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b Gerrit-Change-Number: 78222 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/amd/genoa: Add SMI support
by Varshit Pandya (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Varshit Pandya. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78221?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/genoa: Add SMI support ...................................................................... soc/amd/genoa: Add SMI support Add SMI definitions as per Genoa PPR Doc #55901 Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/genoa/Kconfig A src/soc/amd/genoa/include/soc/smi.h 2 files changed, 185 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/78221/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Gerrit-Change-Number: 78221 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: soc/amd/genoa: Add GPIO definitions
by Varshit Pandya (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Varshit Pandya. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78220?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/genoa: Add GPIO definitions ...................................................................... soc/amd/genoa: Add GPIO definitions Add GPIO definitions as per Genoa PPR Doc #55901 Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- A src/soc/amd/genoa/include/soc/gpio.h 1 file changed, 262 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/78220/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Gerrit-Change-Number: 78220 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/genoa: Enable PM and cf9 IO early
by Varshit Pandya (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#9) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76505?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/genoa: Enable PM and cf9 IO early ...................................................................... soc/amd/genoa: Enable PM and cf9 IO early Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 --- M src/soc/amd/genoa/early_fch.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/76505/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/76505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I05990c2aca40d9cf47a9ebdfd269b80b8f60e300 Gerrit-Change-Number: 76505 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: device/pci_def.h: Add more bits
by Felix Held (Code Review) 06 Oct '23

06 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78237?usp=email ) Change subject: device/pci_def.h: Add more bits ...................................................................... device/pci_def.h: Add more bits Add more fields for PCIe slots status and link control and slot capabilities. Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78237 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/pci_def.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Kyösti Mälkki: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index aa53909..9ecd50a 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -430,6 +430,7 @@ #define PCI_EXP_CLK_PM 0x40000 /* Clock Power Management */ #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_LD 0x10 /* Link Disable */ #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock Configuration */ #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ @@ -437,10 +438,14 @@ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ +#define PCI_EXP_SLTCAP_SPLV 0x7f80 /* Slot Power Limit Value */ +#define PCI_EXP_SLTCAP_SPLS 0x18000 /* Slot Power Limit Scale */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ +#define PCI_EXP_SLTSTA_PDS 0x40 /* Presence Detect Status */ #define PCI_EXP_RTCTL 28 /* Root Control */ #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */ #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */ -- To view, visit https://review.coreboot.org/c/coreboot/+/78237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Gerrit-Change-Number: 78237 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal
by Derek Huang (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Joey Peng, Paul Menzel, Reka Norman. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78146?usp=email ) Change subject: mb/google/dedede/var/boxy: Wait up for 3s for HPD ready signal ...................................................................... Patch Set 8: (4 comments) File src/mainboard/google/dedede/variants/boxy/ramstage.c: https://review.coreboot.org/c/coreboot/+/78146/comment/97f28a98_872135fe : PS8, Line 68: Are you sure we can get the correct gpio state by get_gpio() without configuring the gpio to input? https://review.coreboot.org/c/coreboot/+/78146/comment/48051e03_a5a22ec8 : PS8, Line 70: && !gpio_get(GPIO_USB_C0_HPD) this is redundant. https://review.coreboot.org/c/coreboot/+/78146/comment/9abc33f9_14899ed3 : PS8, Line 74: && !gpio_get(GPIO_USB_C1_HPD this is redundant https://review.coreboot.org/c/coreboot/+/78146/comment/9562d637_3d461fbe : PS8, Line 69: if (display_init_required() : && !gpio_get(GPIO_USB_C0_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms); : } else if (display_init_required() : && !gpio_get(GPIO_USB_C1_HPD)) { : /* This has to be done before FSP-S runs. */ : wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms); : } If only HDMI is connected, these will always timeout and add 6s delay. It's better to check HDMI HPD as well and call wait_for_hpd only when HDMI is not connected. Probably we can do, wait_for_hpd() should return 1 when HPD is detected: ``` if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { /* This has to be done before FSP-S runs. */ if(wait_for_hpd(GPIO_USB_C0_HPD, display_timeout_ms)) return; wait_for_hpd(GPIO_USB_C1_HPD, display_timeout_ms); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208fdf8234886b2ef43a4b972e6682892238e8e9 Gerrit-Change-Number: 78146 Gerrit-PatchSet: 8 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 06 Oct 2023 12:35:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Follow PCH BIOS spec
by Felix Held (Code Review) 06 Oct '23

06 Oct '23

Attention is currently required from: Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78225?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: sb/intel/bd82x6x: Follow PCH BIOS spec ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/southbridge/intel/bd82x6x/early_pch.c: https://review.coreboot.org/c/coreboot/+/78225/comment/4072a09a_76518722 : PS3, Line 139: 0x1e58 might be good to add a define for this to avoid having a magic constant in here to make it a bit more obvious what this is doing. a comment pointing out that this is the case of the UM77 chipset that has less pcie ports would be fine too -- To view, visit https://review.coreboot.org/c/coreboot/+/78225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865818c0c22194fffcb2bbdf8c43737b0dce2307 Gerrit-Change-Number: 78225 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 06 Oct 2023 12:33:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/intel/model_206ax: Only use supported C-states
by Felix Held (Code Review) 06 Oct '23

06 Oct '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78194?usp=email ) Change subject: cpu/intel/model_206ax: Only use supported C-states ...................................................................... cpu/intel/model_206ax: Only use supported C-states When advertising C-state using the ACPI _CST object, make sure to only advertise those that are supported by the CPU. Downgrade if it's not and make sure to not advertise duplicate states. Add debug prints for the finally selected mapping of ACPI C-state vs Intel CPU C-state. Test: Tested on Lenovo X220. All C-states are still advertised as all are supported. Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78194 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_206ax/acpi.c 1 file changed, 59 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index c4f5839..f3bd67b 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -87,23 +87,77 @@ printk(BIOS_DEBUG, "\n"); } +/* + * Returns the supported C-state or the next lower one that + * is supported. + */ +static int get_supported_cstate(int cstate) +{ + uint8_t state, substate; + size_t i; + + assert(cstate < NUM_C_STATES); + + for (i = cstate; i > 0; i--) { + state = (cstate_map[i].resource.addrl >> 4) + 1; + substate = cstate_map[i].resource.addrl & 0xf; + if (cpu_get_c_substate_support(state) > substate) + break; + } + + if (cstate != i) + printk(BIOS_INFO, "Requested C-state %s not supported, using %s instead\n", + c_state_names[cstate], c_state_names[i]); + + return i; +} + static void generate_C_state_entries(const struct device *dev) { struct cpu_intel_model_206ax_config *conf = dev->chip_info; - const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; + int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 }; acpi_cstate_t acpi_cstate_map[ARRAY_SIZE(acpi_cstates)] = { 0 }; /* Count number of active C-states */ int count = 0; for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { - if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) { - acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; - acpi_cstate_map[count].ctype = i + 1; - count++; + /* Remove invalid states */ + if (acpi_cstates[i] >= ARRAY_SIZE(cstate_map)) { + printk(BIOS_ERR, "Invalid C-state in devicetree: %d\n", + acpi_cstates[i]); + acpi_cstates[i] = 0; + continue; + } + /* Skip C0, it's always supported */ + if (acpi_cstates[i] == 0) + continue; + + /* Find supported state. Might downgrade a state. */ + acpi_cstates[i] = get_supported_cstate(acpi_cstates[i]); + + /* Remove duplicate states */ + for (int j = i - 1; j >= 0; j--) { + if (acpi_cstates[i] == acpi_cstates[j]) { + acpi_cstates[i] = 0; + break; + } } } + + /* Convert C-state to ACPI C-states */ + for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) { + if (acpi_cstates[i] == 0) + continue; + acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; + acpi_cstate_map[count].ctype = i + 1; + + count++; + printk(BIOS_DEBUG, "Advertising ACPI C State type C%d as CPU %s\n", + i + 1, c_state_names[acpi_cstates[i]]); + } + acpigen_write_CST_package(acpi_cstate_map, count); } -- To view, visit https://review.coreboot.org/c/coreboot/+/78194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaaee050e0ce3c29c12e97f5819a29f485a7946c2 Gerrit-Change-Number: 78194 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: cpu/intel/model_206ax: Print supported C-states
by Felix Held (Code Review) 06 Oct '23

06 Oct '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78133?usp=email ) Change subject: cpu/intel/model_206ax: Print supported C-states ...................................................................... Patch Set 8: (1 comment) File src/cpu/intel/model_206ax/acpi.c: https://review.coreboot.org/c/coreboot/+/78133/comment/471ab991_22039a9e : PS5, Line 109: > l > That would not result in the same behaviour. […] ah, the acpi resource only having the c stares starting with c1 explains things. with that info the code looks good to me -- To view, visit https://review.coreboot.org/c/coreboot/+/78133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I713712a1a104714cbf3091782e564e7e784cf21d Gerrit-Change-Number: 78133 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Oct 2023 12:28:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit October 2023