coreboot-gerrit October 2023

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78009?usp=email ) Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78009/comment/2d21cc25_290a3ee2 : PS13, Line 13: BUG=b:300690448 > Please add line: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 14 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 04:34:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/google/brox: Create new Brox baseboard
by Shelley Chen (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Paul Menzel, Shelley Chen. Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78009?usp=email to look at the new patch set (#14). Change subject: mb/google/brox: Create new Brox baseboard ...................................................................... mb/google/brox: Create new Brox baseboard This CL is just getting the initial brox framework to get the baseboard building. Copied files from brask baseboard and tried to remove contents of some files like the device tree and memory IDs. Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to DRAM ID 0. BUG=b:300690448 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/brox/Kconfig A src/mainboard/google/brox/Kconfig.name A src/mainboard/google/brox/Makefile.inc A src/mainboard/google/brox/acpi/gps.asl A src/mainboard/google/brox/acpi/gpu_defines.h A src/mainboard/google/brox/acpi/gpu_ec.asl A src/mainboard/google/brox/acpi/gpu_top.asl A src/mainboard/google/brox/acpi/nbci.asl A src/mainboard/google/brox/acpi/nvjt.asl A src/mainboard/google/brox/acpi/nvop.asl A src/mainboard/google/brox/acpi/nvpcf.asl A src/mainboard/google/brox/acpi/peg.asl A src/mainboard/google/brox/acpi/power.asl A src/mainboard/google/brox/acpi/utility.asl A src/mainboard/google/brox/board_info.txt A src/mainboard/google/brox/bootblock.c A src/mainboard/google/brox/chromeos.c A src/mainboard/google/brox/chromeos.fmd A src/mainboard/google/brox/dsdt.asl A src/mainboard/google/brox/ec.c A src/mainboard/google/brox/mainboard.c A src/mainboard/google/brox/romstage.c A src/mainboard/google/brox/smihandler.c A src/mainboard/google/brox/spd/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/Makefile.inc A src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb A src/mainboard/google/brox/variants/baseboard/brox/gma-mainboard.ads A src/mainboard/google/brox/variants/baseboard/brox/gpio.c A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h A src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h A src/mainboard/google/brox/variants/baseboard/brox/memory.c A src/mainboard/google/brox/variants/baseboard/brox/ramstage.c A src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/brox/variants/brox/Makefile.inc A src/mainboard/google/brox/variants/brox/data.vbt A src/mainboard/google/brox/variants/brox/fw_config.c A src/mainboard/google/brox/variants/brox/gpio.c A src/mainboard/google/brox/variants/brox/include/variant/ec.h A src/mainboard/google/brox/variants/brox/include/variant/gpio.h A src/mainboard/google/brox/variants/brox/memory/Makefile.inc A src/mainboard/google/brox/variants/brox/memory/dram_id.generated.txt A src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt A src/mainboard/google/brox/variants/brox/overridetree.cb A src/mainboard/google/brox/variants/brox/ramstage.c A src/mainboard/google/brox/variants/brox/variant.c A src/mainboard/google/brox/wwan_power.asl 46 files changed, 2,801 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/78009/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/78009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98 Gerrit-Change-Number: 78009 Gerrit-PatchSet: 14 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
by Bill XIE (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Bill XIE, Jonathon Hall, Kyösti Mälkki, Nico Huber, Paul Menzel. Hello Jonathon Hall, Nico Huber, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78288?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Jonathon Hall, Verified+1 by build bot (Jenkins) Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume ...................................................................... drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1"), Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via bisect). Further inspection shows that DRAM training result of GM45 is stored in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume to restore, but it will be erased by sanitize_cmos(), which now clears both bank 0 and bank 1, leaving only "untrained" result restored, so s3 resume will fail. However, resetting CMOS seems unnecessary during s3 resume. Now, cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again with these changes. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/drivers/pc80/rtc/option.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/78288/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Gerrit-Change-Number: 78288 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Revert "mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid h...
by Wentao Qin (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Eran Mitrani, Kane Chen, Kun Liu, Tarun. Wentao Qin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78320?usp=email ) Change subject: Revert "mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang" ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: we can merge this CL now -- To view, visit https://review.coreboot.org/c/coreboot/+/78320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4517bbbefe11d95623d7e16a5e4bba2dd6f408e1 Gerrit-Change-Number: 78320 Gerrit-PatchSet: 3 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mike Lee <mike5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 03:37:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Update SD card GPIO settings
by Eric Lai (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Nick Vaccaro, Paul Menzel, Robert Chen, Shawn Ku, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78253?usp=email ) Change subject: mb/google/nissa/var/quandiso: Update SD card GPIO settings ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/quandiso/gpio.c: https://review.coreboot.org/c/coreboot/+/78253/comment/c2465a45_c1d0f940 : PS4, Line 93: PAD_CFG_GPO(GPP_H12, 1, DEEP), > Set high GPP_H12 first is refer from neried and yaviks that same design with SD_CARD. […] okay I see in early table is low. LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/78253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe Gerrit-Change-Number: 78253 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shawn Ku <shawnku(a)chromium.org> Gerrit-Comment-Date: Fri, 13 Oct 2023 03:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya: fix MRC cache failure for hynix parts
by Nick Vaccaro (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Nick Vaccaro, Shelley Chen, Subrata Banik. Hello Nick Vaccaro, Shelley Chen, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78335?usp=email to look at the new patch set (#2). Change subject: mb/google/brya: fix MRC cache failure for hynix parts ...................................................................... mb/google/brya: fix MRC cache failure for hynix parts Set the cs_pi_start_high_in_ect if the DUT is using one of the two following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to set cs_pi_start_high_in_ect when using these parts will result in an MRC cache failure and DUT will fail to boot. BUG=b:292153199 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya variant to kernel. Change-Id: Icb34c7e093e9f030820de7ca627848f0b767fcc4 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/memory.c 1 file changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/78335/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb34c7e093e9f030820de7ca627848f0b767fcc4 Gerrit-Change-Number: 78335 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/google/brya: fix MRC cache failure for hynix parts
by Nick Vaccaro (Code Review) 13 Oct '23

13 Oct '23

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78335?usp=email ) Change subject: mb/google/brya: fix MRC cache failure for hynix parts ...................................................................... mb/google/brya: fix MRC cache failure for hynix parts Set the cs_pi_start_high_in_ect if the DUT is using one of the two following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to set cs_pi_start_high_in_ect when using these parts will result in an MRC cache failure and DUT will fail to boot. BUG=b:292153199 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya variant to kernel. Change-Id: Icb34c7e093e9f030820de7ca627848f0b767fcc4 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/memory.c 1 file changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/78335/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/memory.c b/src/mainboard/google/brya/variants/baseboard/brya/memory.c index bcad9b4..acf8a0f 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/memory.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/memory.c @@ -66,8 +66,82 @@ .ect = 1, /* Enable Early Command Training */ }; +static const struct mb_cfg hynix_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, + .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, + }, + .ddr1 = { + .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, + .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, + .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, + }, + .ddr3 = { + .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, + .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, + .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, + }, + .ddr5 = { + .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, + .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, + }, + .ddr6 = { + .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, + .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, + }, + .ddr7 = { + .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, + .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .ect = 1, /* Enable Early Command Training */ + + .cs_pi_start_high_in_ect = 1, +}; + const struct mb_cfg *__weak variant_memory_params(void) { + const char *part_num = mainboard_get_dram_part_num(); + const char *hynix_mem1 = "H54G46CYRBX267"; + const char *hynix_mem2 = "H54G56CYRBX247"; + + if (part_num) { + if (!strcmp(part_num, hynix_mem1) || !strcmp(part_num, hynix_mem2)) { + printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix memory\n"); + return &hynix_memcfg; + } + } return &baseboard_memcfg; } -- To view, visit https://review.coreboot.org/c/coreboot/+/78335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb34c7e093e9f030820de7ca627848f0b767fcc4 Gerrit-Change-Number: 78335 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/rex/var/rex: Configure PL4 to 64W if battery status is invalid
by Caveh Jalali (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Brandon Breitenstein, Eran Mitrani, Hannah Williams, Jamie Ryu, Kapil Porwal, Subrata Banik, Sukumar Ghorai, Tarun. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78322?usp=email ) Change subject: mb/google/rex/var/rex: Configure PL4 to 64W if battery status is invalid ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/rex/variants/baseboard/rex/ramstage.c: https://review.coreboot.org/c/coreboot/+/78322/comment/181cb4e6_333fe89c : PS5, Line 25: p > Acknowledged 'optimized' sounds like the preferred/nominal profile, but this is really the fail-safe profile. https://review.coreboot.org/c/coreboot/+/78322/comment/b01d8331_3d560df4 : PS5, Line 48: battery_status > What is the condition we are going to check to limit PL4 now? Are we going to consider Battery level […] `EC_BATT_FLAG_LEVEL_CRITICAL` means we're below `CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE` (default 4%) at which point we notify the AP with `EC_HOST_EVENT_BATTERY_CRITICAL` in the hopes the user is notified before we force a shutdown or things go dark. there are a bunch of additional thresholds that go into deciding to shut down the AP... -- To view, visit https://review.coreboot.org/c/coreboot/+/78322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8 Gerrit-Change-Number: 78322 Gerrit-PatchSet: 5 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 02:39:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/quandiso: Update SD card GPIO settings
by Robert Chen (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Eric Lai, Nick Vaccaro, Paul Menzel, Shawn Ku, Subrata Banik. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78253?usp=email ) Change subject: mb/google/nissa/var/quandiso: Update SD card GPIO settings ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/quandiso/gpio.c: https://review.coreboot.org/c/coreboot/+/78253/comment/d5ae6b0f_884ce163 : PS4, Line 93: PAD_CFG_GPO(GPP_H12, 1, DEEP), > Could you post the issue link to me? I go the that number is not your issue. Set high GPP_H12 first is refer from neried and yaviks that same design with SD_CARD. Sorry for the bug number mistake, right link is to b:296506936. Quandiso: Create coreboot variant -- To view, visit https://review.coreboot.org/c/coreboot/+/78253?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe Gerrit-Change-Number: 78253 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shawn Ku <shawnku(a)chromium.org> Gerrit-Comment-Date: Fri, 13 Oct 2023 02:28:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify GPIOs to remove TOF function
by Dtrain Hsu (Code Review) 13 Oct '23

13 Oct '23

Attention is currently required from: Chen-Tsung Hsieh, Derek Huang, Ian Feng, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78147?usp=email ) Change subject: mb/google/nissa/var/craaskov: Modify GPIOs to remove TOF function ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/craaskov/gpio.c: https://review.coreboot.org/c/coreboot/+/78147/comment/8692cd1b_a79148be : PS1, Line 14: /* B5 : GPP_B5 ==> NC */ Here is disable i2c bus, should we also disable i2c bus in overridetree.cb? ``` .i2c[2] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 158, .scl_hcnt = 79, .sda_hold = 7, } }, ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443 Gerrit-Change-Number: 78147 Gerrit-PatchSet: 1 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Fri, 13 Oct 2023 02:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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