Zoltan Baldaszti has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45829 )
Change subject: Documentation: added more payload links and descriptions
......................................................................
Documentation: added more payload links and descriptions
Change-Id: I13c10edbc7fbb7017641ab025982c658cbeb3610
Signed-off-by: Zoltan Baldaszti <bztemail(a)gmail.com>
---
M Documentation/payloads.md
1 file changed, 35 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/45829/1
diff --git a/Documentation/payloads.md b/Documentation/payloads.md
index eee841e..bee8393 100644
--- a/Documentation/payloads.md
+++ b/Documentation/payloads.md
@@ -23,17 +23,45 @@
coreboot payload, but these days this function is available directly in the
CorebootPayloadPkg part of its source tree.
+## iPXE
+
+[iPXE](https://ipxe.org) is the leading open source network boot firmware.
+It provides a full PXE Implementation enchaced with additional features such
+as booting from HTTP, iSCSI, FCoE, AoE, wireless, WAN, infiniband.
+
## GRUB2
-GRUB2 was originally written as a bootloader and that's its most popular
-purpose, but it can also be compiled as a coreboot payload.
+[GRUB2](https://www.gnu.org/software/grub) was originally written as a
+bootloader and that's its most popular purpose, but it can also be compiled
+as a coreboot payload.
+
+## U-Boot
+
+[U-Boot](https://www.denx.de/wiki/U-Boot) is a boot loader for Embedded boards
+based on PowerPC, ARM, MIPS and several other processors, which can be
+installed in a boot ROM and used to initialize and test the hardware or to
+download and run application code.
+
+## FILO
+
+[FILO](https://www.coreboot.org/FILO) loads boot images from local filesystem,
+without help from legacy BIOS services. Expected usage is to flash it into
+the BIOS ROM together with coreboot.
+
+## BOOTBOOT
+
+[BOOTBOOT](https://gitlab.com/bztsrc/bootboot) is a multi-platform,
+architecture agnostic boot protocol. The protocol describes how to boot an
+ELF64 or PE32+ executable inside an initial ram disk image into clean 64 bit
+mode. This version uses libpayload to do that. Initrd can be in ROM or on
+disk a GPT partition or a file on a FAT formatted ESP partition.
## Linux
-There are several projects using Linux as a payload (which was the
-configuration that gave coreboot its original name, LinuxBIOS). That kernel is
-often rather small and serves to load a current kernel from somewhere, e.g.
-disk or network, and run that through the kexec mechanism.
+There are several projects using [Linux](https://kernel.org) as a payload
+(which was the configuration that gave coreboot its original name, LinuxBIOS).
+That kernel is often rather small and serves to load a current kernel from
+somewhere, e.g. disk or network, and run that through the kexec mechanism.
Two aspects emphasized by proponents of Linux-as-a-payload are the
availability of well-tested, battle-hardened drivers (as compared to
@@ -51,4 +79,4 @@
For more details have a look at [heads-wiki].
[Heads]: https://github.com/osresearch/heads
-[heads-wiki]: http://osresearch.net/
\ No newline at end of file
+[heads-wiki]: http://osresearch.net/
--
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Gerrit-Owner: Zoltan Baldaszti <bztemail(a)gmail.com>
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49056 )
Change subject: [TEST] abuild: Default to !CHROMEOS
......................................................................
[TEST] abuild: Default to !CHROMEOS
Change-Id: I9ae4bc22f70be5b8d8efa35f0cc8aa2d36a5531a
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M util/abuild/abuild
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/49056/1
diff --git a/util/abuild/abuild b/util/abuild/abuild
index 408de12..59da54c 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -655,7 +655,7 @@
clean_objs=false
verboseopt='V=0'
customizing=""
-configoptions=""
+configoptions="# CONFIG_CHROMEOS is not set\n"
# testclass needs to be undefined if not used for variable expansion to work
unset testclass
while true ; do
--
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Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37628 )
Change subject: soc/intel/common: Add romstage common stage file
......................................................................
soc/intel/common: Add romstage common stage file
This patch will ensures all intel soc is using common stage
files to make coreboot design flow align across all socs.
CPU, SA, PCH, MCH programming sequence might be different between
socs but the function call should route from same location across
all soc.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I06d43ac29f5e87ce731a470e5e145adea07ece4c
---
M src/cpu/intel/car/romstage.c
A src/soc/intel/common/basecode/include/intelbasecode/romstage.h
A src/soc/intel/common/basecode/romstage/Makefile.inc
A src/soc/intel/common/basecode/romstage/romstage.c
4 files changed, 162 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/37628/1
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 1f8eb9a..55d3c9d 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -52,9 +52,6 @@
for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
- if (CONFIG(VBOOT_EARLY_EC_SYNC))
- vboot_sync_ec();
-
mainboard_romstage_entry();
/* Check the stack. */
@@ -64,9 +61,6 @@
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}
- if (CONFIG(SMM_TSEG))
- smm_list_regions();
-
prepare_and_run_postcar(&early_mtrrs);
/* We do not return here. */
}
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/romstage.h b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
new file mode 100644
index 0000000..0cebbbf
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/romstage.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+#define SOC_INTEL_COMMON_BASECODE_ROMSTAGE_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+struct romstage_ops {
+ void (*soc_early_init)(void);
+ void (*soc_init)(void);
+ void (*pch_early_init)(void);
+ void (*pch_init)(void);
+ void (*cpu_early_init)(void);
+ void (*cpu_init)(void);
+ bool (*is_s3wake)(void);
+ void (*soc_mem_init_params)(FSP_M_CONFIG *mupd);
+};
+
+/* SoC Override function */
+struct romstage_ops *soc_get_ops(void);
+
+#endif
diff --git a/src/soc/intel/common/basecode/romstage/Makefile.inc b/src/soc/intel/common/basecode/romstage/Makefile.inc
new file mode 100644
index 0000000..29763fb
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += romstage.c
diff --git a/src/soc/intel/common/basecode/romstage/romstage.c b/src/soc/intel/common/basecode/romstage/romstage.c
new file mode 100644
index 0000000..55c4ab5
--- /dev/null
+++ b/src/soc/intel/common/basecode/romstage/romstage.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <romstage_common.h>
+#include <cpu/x86/pae.h>
+#include <intelbasecode/romstage.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/romstage.h>
+
+static const struct romstage_ops s_romstage_ops;
+
+__weak struct romstage_ops *soc_get_ops(void)
+{
+ return (struct romstage_ops *)&s_romstage_ops;
+}
+
+void romstage_early_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_early_init();
+ rs_ops->pch_early_init();
+ rs_ops->cpu_early_init();
+}
+
+void romstage_init(void)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ rs_ops->soc_init();
+ rs_ops->pch_init();
+ rs_ops->cpu_init();
+}
+
+void romstage_cmn_soc_early_init(void)
+{
+ systemagent_early_init();
+ heci_init(HECI1_BASE_ADDRESS);
+}
+
+void romstage_cmn_soc_init(void)
+{
+}
+
+void romstage_cmn_pch_early_init(void)
+{
+}
+
+void romstage_cmn_cpu_early_init(void)
+{
+}
+
+void romstage_cmn_pch_init(void)
+{
+}
+
+void romstage_cmn_cpu_init(void)
+{
+}
+
+bool romstage_cmn_is_s3wake(void)
+{
+ struct chipset_power_state *ps = pmc_get_power_state();
+ return pmc_fill_power_state(ps) == ACPI_S3;
+}
+
+void romstage_cmn_soc_mem_init_param(FSP_M_CONFIG *m_cfg)
+{
+}
+
+static const struct romstage_ops s_romstage_ops = {
+ &romstage_cmn_soc_early_init,
+ &romstage_cmn_soc_init,
+ &romstage_cmn_pch_early_init,
+ &romstage_cmn_pch_init,
+ &romstage_cmn_cpu_early_init,
+ &romstage_cmn_cpu_init,
+ &romstage_cmn_is_s3wake,
+ &romstage_cmn_mb_mem_init_param,
+ &romstage_cmn_soc_mem_init_param
+};
+
+/*
+ Main romstage function
+*/
+asmlinkage void mainboard_romstage_entry(void)
+{
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec(rs_ops->fill_power_state());
+
+ romstage_early_init();
+ romstage_init();
+ fsp_memory_init(rs_ops->is_s3wake());
+
+ if (CONFIG(SMM_TSEG))
+ smm_list_regions();
+}
+
+/*
+ Callback function for FSP memory initialization
+*/
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+ struct romstage_ops *rs_ops = soc_get_ops();
+
+ FSP_M_CONFIG *m_cfg;
+ rs_ops->soc_mem_init_params(m_cfg);
+ mainboard_memory_init_params(m_cfg);
+}
+
--
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39043 )
Change subject: [TESTME]lenovo/x220: Attempt to fix broken DRAM init
......................................................................
[TESTME]lenovo/x220: Attempt to fix broken DRAM init
Enable power on WWAN as it has SMBUS connected.
Might resolv an issue where DRAM init fails as no EEPROM is
found on the bus.
Untested.
Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/ec/lenovo/h8/Makefile.inc
M src/mainboard/lenovo/x220/early_init.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39043/1
diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc
index 51c11be..9c8687a 100644
--- a/src/ec/lenovo/h8/Makefile.inc
+++ b/src/ec/lenovo/h8/Makefile.inc
@@ -18,6 +18,8 @@
ramstage-y += panic.c
endif
+romstage += wwan.c
+
ramstage-y += h8.c
ramstage-y += bluetooth.c
ramstage-y += wwan.c
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index 3429c1b..ae16f0c 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -24,6 +24,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <cpu/x86/msr.h>
+#include <ec/lenovo/h8/h8.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
@@ -74,6 +75,18 @@
*pei_data = pei_data_template;
}
+void mainboard_early_init(int s3_resume)
+{
+ /*
+ * The WWAN slot has SMBUS connected. Turn on power to make sure
+ * SMBUS is usable and DRAM init will succeed.
+ * ramstage will turn it off, in case it's not needed.
+ * TODO: Does GPIO42 (SMB_3B_EN) help here?
+ */
+ if (h8_has_wwan())
+ h8_wwan_enable(true);
+}
+
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd (&spd[0], 0x50, id_only);
--
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