coreboot-gerrit August 2022

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Change in ...coreboot[master]: libpayload: Draw time_t and suseconds_t into sys/types.h
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31379 Change subject: libpayload: Draw time_t and suseconds_t into sys/types.h ...................................................................... libpayload: Draw time_t and suseconds_t into sys/types.h These are not architecture specific and were the only reason to include `arch/types.h` in `sys/types.h`. Beware this may break payloads that assume non-standard definitions in `sys/types.h`. Change-Id: I00d513a4775b013221df98d3d96c096320663cdd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/include/arm/arch/types.h M payloads/libpayload/include/arm64/arch/types.h M payloads/libpayload/include/mips/arch/types.h M payloads/libpayload/include/sys/types.h M payloads/libpayload/include/x86/arch/types.h 5 files changed, 2 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/31379/1 diff --git a/payloads/libpayload/include/arm/arch/types.h b/payloads/libpayload/include/arm/arch/types.h index 1bd815b..641fb0a 100644 --- a/payloads/libpayload/include/arm/arch/types.h +++ b/payloads/libpayload/include/arm/arch/types.h @@ -50,9 +50,6 @@ typedef signed long long int64_t; typedef signed long long s64; -typedef long time_t; -typedef long suseconds_t; - #ifndef NULL #define NULL ((void *)0) #endif diff --git a/payloads/libpayload/include/arm64/arch/types.h b/payloads/libpayload/include/arm64/arch/types.h index 1bd815b..641fb0a 100644 --- a/payloads/libpayload/include/arm64/arch/types.h +++ b/payloads/libpayload/include/arm64/arch/types.h @@ -50,9 +50,6 @@ typedef signed long long int64_t; typedef signed long long s64; -typedef long time_t; -typedef long suseconds_t; - #ifndef NULL #define NULL ((void *)0) #endif diff --git a/payloads/libpayload/include/mips/arch/types.h b/payloads/libpayload/include/mips/arch/types.h index afa3a37..32537b8 100644 --- a/payloads/libpayload/include/mips/arch/types.h +++ b/payloads/libpayload/include/mips/arch/types.h @@ -62,9 +62,6 @@ typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -typedef long time_t; -typedef long suseconds_t; - #ifndef NULL #define NULL ((void *)0) #endif diff --git a/payloads/libpayload/include/sys/types.h b/payloads/libpayload/include/sys/types.h index 0ed4975..f7e0598 100644 --- a/payloads/libpayload/include/sys/types.h +++ b/payloads/libpayload/include/sys/types.h @@ -30,7 +30,8 @@ #ifndef _SYS_TYPES_H #define _SYS_TYPES_H -#include <arch/types.h> +typedef long time_t; +typedef long suseconds_t; typedef signed long int off_t; diff --git a/payloads/libpayload/include/x86/arch/types.h b/payloads/libpayload/include/x86/arch/types.h index 1bd815b..641fb0a 100644 --- a/payloads/libpayload/include/x86/arch/types.h +++ b/payloads/libpayload/include/x86/arch/types.h @@ -50,9 +50,6 @@ typedef signed long long int64_t; typedef signed long long s64; -typedef long time_t; -typedef long suseconds_t; - #ifndef NULL #define NULL ((void *)0) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00d513a4775b013221df98d3d96c096320663cdd Gerrit-Change-Number: 31379 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: intel/apollolake: mark read only SRAM as reserved
by Christian Gmeiner (Code Review) 10 Jun '23

10 Jun '23

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31462 Change subject: intel/apollolake: mark read only SRAM as reserved ...................................................................... intel/apollolake: mark read only SRAM as reserved Change-Id: I0ccb40f30e8596b3f57e30901efdbd5d6f9529f1 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- M src/soc/intel/apollolake/mmap_boot.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/31462/1 diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 1c3077e..a1de8ea 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -18,6 +18,7 @@ #include <arch/early_variables.h> #include <boot_device.h> +#include <bootmem.h> #include <cbfs.h> #include <commonlib/region.h> #include <console/console.h> @@ -146,3 +147,11 @@ .name = "IAFW Locator", .locate = iafw_boot_region_properties, }; + +void bootmem_platform_add_ranges(void) +{ + const int size = 256 * KiB; + + /* read only SRAM */ + bootmem_add_range(0x100000000 - size, size, BM_MEM_RESERVED); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/31462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ccb40f30e8596b3f57e30901efdbd5d6f9529f1 Gerrit-Change-Number: 31462 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Gmeiner <christian.gmeiner(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: asrock/e350m1: Enable Core Performance Boost
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31417 Change subject: asrock/e350m1: Enable Core Performance Boost ...................................................................... asrock/e350m1: Enable Core Performance Boost Allow one core to temporarily exceed the maximum frequency. [1]: https://3mdeb.com/firmware/amd-cpu-boost/ Change-Id: If76389a16aed9df86f43e3aaed41a196288c3bb2 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asrock/e350m1/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31417/1 diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 14621e0..dc4df43 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -151,7 +151,7 @@ #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -- To view, visit https://review.coreboot.org/c/coreboot/+/31417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76389a16aed9df86f43e3aaed41a196288c3bb2 Gerrit-Change-Number: 31417 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: util: add a tool to dump and insert MEC1322 firmware
by Iru Cai (vimacs) (Code Review) 22 May '23

22 May '23

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41393 to review the following change. Change subject: util: add a tool to dump and insert MEC1322 firmware ...................................................................... util: add a tool to dump and insert MEC1322 firmware Refer to chip/mec1322/util/pack_ec.py in chromeec project for MEC1322 firmware format. Tested on the backup files of the system and private flashes of HP EliteBook 820 G1. This tool can dump the EC firmware from both flashes and insert the EC firmware to the original ROM file and make the ROM unchanged. It needs to be tested on real hardware to see if a modified ROM with a re-inserted EC firmware works. Change-Id: I999bf0289216bf72c4f8f19182c7670d7008b5f9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/README.md A util/mec1322/Makefile A util/mec1322/mec1322.c 3 files changed, 324 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41393/1 diff --git a/util/README.md b/util/README.md index 8b05f6f..672d1da 100644 --- a/util/README.md +++ b/util/README.md @@ -63,6 +63,7 @@ * __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C` * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for partial deblobbing of Intel ME/TXE firmware images `Python` +* __mec1322__ - Dumps and inserts MEC1322 EC firmware `C` * __mma__ - Memory Margin Analysis automation tests `Bash` * __msrtool__ - Dumps chipset-specific MSR registers. `C` * __mtkheader__ - Generate MediaTek bootload header. `Python2` diff --git a/util/mec1322/Makefile b/util/mec1322/Makefile new file mode 100644 index 0000000..4ccbe92 --- /dev/null +++ b/util/mec1322/Makefile @@ -0,0 +1,21 @@ +## This file is part of the coreboot project. +## +## SPDX-License-Identifier: GPL-2.0-or-later + +obj = mec1322 +HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) + +ifeq ($(VERIFY_SIG),1) + CFLAGS += -DVERIFY_SIG + LIBS := -lcrypto +endif + +all: $(obj) + +%: %.c + $(HOSTCC) $(CFLAGS) -Wall -o $@ $< $(LIBS) + +clean: + rm -f $(obj) + +.PHONY: all clean diff --git a/util/mec1322/mec1322.c b/util/mec1322/mec1322.c new file mode 100644 index 0000000..7ee83bb --- /dev/null +++ b/util/mec1322/mec1322.c @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdio.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> + +#ifdef VERIFY_SIG +#include <openssl/obj_mac.h> +#include <openssl/rsa.h> +#include <openssl/sha.h> +#endif + +void usage(void) +{ + fprintf(stderr, + "Usage:\n" + "\tmec1322 dump [-s <flash size>] [-o <outfile>] <infile>\n" + "\tmec1322 insert [-s <flash size>] [-f <image>] <infile> <header_loc>\n"); + + exit(1); +} + +const int SPI_CLOCK_LIST[] = {48, 24, 12, 8}; +const uint8_t SPI_READ_CMD_LIST[] = {0x3, 0xb, 0x3b}; + +// FIXME: uint32_t cannot be used directly on big endian systems +struct mec1322_header { + uint8_t sig[6]; // "CSMS\0\0" + uint8_t spi_clk; + uint8_t spi_read_cmd; + uint32_t load_addr; + uint32_t entry_point; + uint16_t payload_blks; // payload_len >> 6 + uint8_t padding0[2]; + uint32_t payload_offset; + uint8_t padding1[8]; + uint8_t payload_key_exp[16]; // @0x20 + uint8_t payload_key_modulus[256]; // @0x30 +}; + +uint8_t crc8(const uint8_t *data, size_t len) +{ + const uint8_t CRC_TABLE[] = {0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, + 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d}; + uint8_t crc = 0; + for (size_t i = 0; i < len; i++) { + uint8_t v = data[i]; + crc = (crc << 4) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); + crc = (crc << 4) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); + } + return crc ^ 0x55; +} + +// return the total length of the firmware, including header, +// header_signature, and payload +// return 0 if there's error +size_t parse_header(const struct mec1322_header *hdr) +{ + if (memcmp(hdr->sig, "CSMS", 4) != 0) { + fprintf(stderr, "MEC1322 header signature error!\n"); + return 0; + } + + printf("SPI clock = %hhd MHz\n", SPI_CLOCK_LIST[hdr->spi_clk]); + printf("SPI read cmd = 0x%hhx\n", SPI_READ_CMD_LIST[hdr->spi_read_cmd]); + printf("load address = 0x%x\n", hdr->load_addr); + printf("entry point = 0x%x\n", hdr->entry_point); + size_t payload_len = (size_t)hdr->payload_blks * 64; + printf("payload length = 0x%lx\n", payload_len); + printf("payload offset = 0x%x\n", hdr->payload_offset); + return payload_len + hdr->payload_offset; +} + +int verify_payload_signature(const struct mec1322_header *hdr, void *payload, + const uint8_t *sig) +{ +#ifdef VERIFY_SIG + uint8_t hash[32]; + uint8_t sigrev[256]; + + for (size_t i = 0; i < 256; i++) + sigrev[i] = sig[255 - i]; + + RSA *rsa = RSA_new(); + BIGNUM *modulus = BN_lebin2bn(hdr->payload_key_modulus, 256, NULL); + BIGNUM *exp = BN_lebin2bn(hdr->payload_key_exp, 8, NULL); + RSA_set0_key(rsa, modulus, exp, NULL); + + SHA256(payload, (size_t)(hdr->payload_blks) * 64, hash); + + int v = RSA_verify(NID_sha256, hash, 32, sigrev, 256, rsa); + if (!v) + fprintf(stderr, "MEC1322 payload RSA signature error!\n"); + else + printf("MEC1322 payload RSA signature matches the payload.\n"); + + return v; +#else + fprintf(stderr, + "** MEC1322 payload signature verification is not enabled.\n" + "** You can run `make VERIFY_SIG=1` to enable it.\n"); + return 1; +#endif +} + +int mec1322_dump(int argc, char *argv[]) +{ + FILE *infile, *outfile = NULL; + long spisize = 0; + + while (argc > 2) { + if (strcmp(argv[0], "-s") == 0) { + spisize = strtol(argv[1], NULL, 0); + argc -= 2; + argv += 2; + continue; + } + if (strcmp(argv[0], "-o") == 0) { + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Fail to open file %s!\n", argv[1]); + exit(1); + } + argc -= 2; + argv += 2; + continue; + } + // otherwise, print usage and exit + usage(); + } + + if (argc != 1) + usage(); + + // without the above options, it's the input file + infile = fopen(argv[0], "r"); + if (infile == NULL) { + fprintf(stderr, "Fail to open file %s!\n", argv[0]); + exit(1); + } + + if (spisize == 0) { + fseek(infile, -1, SEEK_END); + spisize = ftell(infile) + 1; + + printf("Input file size is 0x%lx.\n", spisize); + } + + // read MEC1322 firmware tag + fseek(infile, -256, SEEK_END); + uint8_t fwTag[4]; + uint32_t header_loc; + fread(fwTag, 1, 4, infile); + + if (crc8(fwTag, 3) == fwTag[3]) { + header_loc = (((uint32_t)fwTag[0]) << 8) | (((uint32_t)fwTag[1]) << 16) + | (((uint32_t)fwTag[2]) << 24); + printf("MEC1322 firmware header location is 0x%x.\n", header_loc); + } else { + fprintf(stderr, "MEC1322 tag CRC8 error!\n"); + return 1; + } + + // we use the distance of header_loc to end when seeking + struct mec1322_header hdr; + fseek(infile, header_loc - spisize, SEEK_END); + fread(&hdr, 1, sizeof(hdr), infile); + size_t fwlen = parse_header(&hdr); + if (fwlen == 0) { + fprintf(stderr, "Error parsing MEC1322 firmware header!\n"); + return 1; + } + + if (outfile) { + fseek(infile, header_loc - spisize, SEEK_END); + void *image = malloc(fwlen); + fread(image, 1, fwlen, infile); + fwrite(image, 1, fwlen, outfile); + + uint8_t rsasig[256]; + fread(rsasig, 1, 256, infile); + fwrite(rsasig, 1, 256, outfile); + + if (!verify_payload_signature(&hdr, image + hdr.payload_offset, rsasig)) + return 1; + + free(image); + fclose(outfile); + } + + fclose(infile); + return 0; +} + +int mec1322_insert(int argc, char *argv[]) +{ + FILE *infile, *ecfile = NULL; + void *image = NULL; + size_t fwlen; + long spisize = 0; + long header_loc; + + if (argc < 2) + usage(); + + while (argc > 2) { + if (strcmp(argv[0], "-s") == 0) { + spisize = strtol(argv[1], NULL, 0); + argc -= 2; + argv += 2; + continue; + } + if (strcmp(argv[0], "-f") == 0) { + ecfile = fopen(argv[1], "r"); + if (ecfile == NULL) { + fprintf(stderr, "Fail to open EC file %s!\n", argv[1]); + return 1; + } + argc -= 2; + argv += 2; + continue; + } + usage(); + } + + if (argc != 2) + usage(); + + infile = fopen(argv[0], "r+"); + header_loc = strtol(argv[1], NULL, 0); + + if (infile == NULL) { + fprintf(stderr, "Fail to open firmware image %s!\n", argv[1]); + return 1; + } + + if (spisize == 0) { + fseek(infile, -1, SEEK_END); + spisize = ftell(infile) + 1; + + printf("Input file size is 0x%lx.\n", spisize); + } + + if (ecfile != NULL) { + struct mec1322_header hdr; + fread(&hdr, 1, sizeof(hdr), ecfile); + fwlen = parse_header(&hdr); + + if (fwlen == 0) { + fprintf(stderr, "Error parsing MEC1322 firmware header!\n"); + return 1; + } + fseek(ecfile, 0, SEEK_SET); + size_t totallen = fwlen + 256; // firmware length with signature + image = malloc(totallen); + fread(image, 1, totallen, ecfile); + fclose(ecfile); + + if (!verify_payload_signature(&hdr, image + hdr.payload_offset, image + fwlen)) + return 1; + + fwlen = totallen; + } + + if (header_loc & 0xff) { + fprintf(stderr, "Header location should be aligned to 256 bytes!\n"); + return 1; + } + uint8_t fwTag[4] = {header_loc >> 8, header_loc >> 16, header_loc >> 24}; + fwTag[3] = crc8(fwTag, 3); + + // write tag + fseek(infile, -256, SEEK_END); + fwrite(fwTag, 1, 4, infile); + + // if EC image is given, write EC image + if (image) { + fseek(infile, header_loc - spisize, SEEK_END); + fwrite(image, 1, fwlen, infile); + free(image); + } + + fclose(infile); + + return 0; +} + +int main(int argc, char *argv[]) +{ + if (argc < 3) + usage(); + + if (strcmp(argv[1], "dump") == 0) + return mec1322_dump(argc - 2, argv + 2); + + if (strcmp(argv[1], "insert") == 0) + return mec1322_insert(argc - 2, argv + 2); + + // no action provided + usage(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999bf0289216bf72c4f8f19182c7670d7008b5f9 Gerrit-Change-Number: 41393 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: drivers/intel/gma: Move IGD OpRegion to CBMEM
by Nico Huber (Code Review) 18 May '23

18 May '23

Hello Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40724 to review the following change. Change subject: drivers/intel/gma: Move IGD OpRegion to CBMEM ...................................................................... drivers/intel/gma: Move IGD OpRegion to CBMEM It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/x4x/gma.c M src/soc/intel/apollolake/graphics.c M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/broadwell/acpi/globalnvs.asl M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/include/soc/nvs.h M src/soc/intel/cannonlake/graphics.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/icelake/graphics.c M src/soc/intel/jasperlake/graphics.c M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/tigerlake/graphics.c M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/nvs.h M src/southbridge/intel/i82801dx/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/nvs.h M src/southbridge/intel/ibexpeak/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/nvs.h 41 files changed, 82 insertions(+), 1,236 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/40724/1 diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 56449d0..764af46 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -69,7 +69,7 @@ } /* Write ASLS PCI register and prepare SWSCI register. */ -void intel_gma_opregion_register(uintptr_t opregion) +static void intel_gma_opregion_register(uintptr_t opregion) { struct device *igd; u16 reg16; @@ -106,17 +106,16 @@ } /* Restore ASLS register on S3 resume and prepare SWSCI. */ -void intel_gma_restore_opregion(void) +static enum cb_err intel_gma_restore_opregion(void) { - if (acpi_is_wakeup_s3()) { - const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - uintptr_t aslb; - - if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs))) - intel_gma_opregion_register(aslb); - else - printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n"); + const igd_opregion_t *const opregion = cbmem_find(CBMEM_ID_IGD_OPREGION); + if (!opregion) { + printk(BIOS_ERR, "GMA: Failed to find IGD OpRegion.\n"); + return CB_ERR; } + /* Write ASLS PCI register and prepare SWSCI register. */ + intel_gma_opregion_register((uintptr_t)opregion); + return CB_SUCCESS; } static enum cb_err vbt_validate(struct region_device *rdev) @@ -236,14 +235,17 @@ } /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ -enum cb_err -intel_gma_init_igd_opregion(igd_opregion_t *opregion) +enum cb_err intel_gma_init_igd_opregion(void) { + igd_opregion_t *opregion; struct region_device rdev; optionrom_vbt_t *vbt = NULL; optionrom_vbt_t *ext_vbt; bool found = false; + if (acpi_is_wakeup_s3()) + return intel_gma_restore_opregion(); + /* Search for vbt.bin in CBFS. */ if (locate_vbt_cbfs(&rdev) == CB_SUCCESS && vbt_validate(&rdev) == CB_SUCCESS) { @@ -285,6 +287,12 @@ return CB_ERR; } + opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion)); + if (!opregion) { + printk(BIOS_ERR, "GMA: Failed to add IGD OpRegion to CBMEM.\n"); + return CB_ERR; + } + memset(opregion, 0, sizeof(igd_opregion_t)); memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 4967691..69c7bc2 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -243,11 +243,7 @@ u8 coreblock_biossignon[155]; } __packed optionrom_vbt_t; -void intel_gma_opregion_register(uintptr_t opregion); -void intel_gma_restore_opregion(void); -uintptr_t gma_get_gnvs_aslb(const void *gnvs); -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb); -enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion); +enum cb_err intel_gma_init_igd_opregion(void); /* * Returns the CBFS filename of the VBT blob. diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 25f7518..a517622 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -32,19 +32,6 @@ write32(res2mmio(gtt_res, reg, 0), data); } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = @@ -205,7 +192,7 @@ } } - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *device) @@ -215,32 +202,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -258,7 +219,6 @@ .init = gma_func0_init, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c6b8fab..f00f8a7 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -210,19 +210,6 @@ return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void power_well_enable(void) { gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE); @@ -510,7 +497,7 @@ gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) @@ -520,30 +507,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -555,7 +518,6 @@ .init = gma_func0_init, .acpi_fill_ssdt = gma_generate_ssdt, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 8a19b3e..794267c 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -44,19 +44,6 @@ #define DEFAULT_BLC_PWM 180 -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; @@ -709,7 +696,7 @@ pci_dev_init(dev); } - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } /* This doesn't reclaim stolen UMA memory, but IGD could still @@ -764,32 +751,6 @@ pci_dev_read_resources(dev); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -808,7 +769,6 @@ .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index c8bbbfd..49068b1 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -65,19 +65,6 @@ return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_ironlake_config *conf = dev->chip_info; @@ -181,7 +168,7 @@ gma_pm_init_post_vbios(dev); gma_enable_swsci(); - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_read_resources(struct device *dev) @@ -210,32 +197,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct pci_operations gma_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -247,7 +208,6 @@ .acpi_fill_ssdt = gma_generate_ssdt, .init = gma_func0_init, .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d398b55..0d4e34d 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -43,19 +43,6 @@ static struct resource *gtt_res = NULL; static struct resource *mmio_res = NULL; -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static int gtt_setup(u8 *mmiobase) { u32 gttbase; @@ -275,31 +262,7 @@ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW"); } - intel_gma_restore_opregion(); -} - -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; + intel_gma_init_igd_opregion(); } static const char *gma_acpi_name(const struct device *dev) @@ -318,7 +281,6 @@ .init = gma_func0_init, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 5c4f548..7a7a767 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -303,19 +303,6 @@ return 0; } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_pm_init_pre_vbios(struct device *dev) { u32 reg32; @@ -637,7 +624,7 @@ } gma_enable_swsci(); - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *device) @@ -647,30 +634,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -702,7 +665,6 @@ .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index f5335ec..133008a 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -28,19 +28,6 @@ #define BASE_FREQUENCY 96000 -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gma_func0_init(struct device *dev) { u32 reg32; @@ -67,7 +54,7 @@ pci_dev_init(dev); } - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_func0_disable(struct device *dev) @@ -87,32 +74,6 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static const char *gma_acpi_name(const struct device *dev) { return "GFX0"; @@ -131,7 +92,6 @@ .ops_pci = &gma_pci_ops, .disable = gma_func0_disable, .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 033b300..36e0a26 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -50,21 +50,6 @@ /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } -} -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - /* FIXME: Add platform specific mailbox initialization */ - - current += sizeof(igd_opregion_t); - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 4aa600f..83d7f46 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -54,48 +54,6 @@ TOLM, 32, // 0x34 - Top of Low Memory CBMC, 32, // 0x38 - coreboot mem console pointer - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 64c9061..9b9679f 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -353,19 +353,6 @@ } } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ @@ -382,8 +369,7 @@ /* Post VBIOS Init */ gfx_post_vbios_init(dev); - /* Restore opregion on S3 resume */ - intel_gma_restore_opregion(); + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) @@ -393,39 +379,12 @@ drivers_intel_gma_displays_ssdt_generate(&chip->gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; -} - static struct device_operations gfx_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, .ops_pci = &soc_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index df81573..e7c64b9 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -47,40 +47,7 @@ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 unused[76]; /* ChromeOS specific (0x100-0xfff)*/ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1e6cea2..2bcc873 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -461,14 +461,6 @@ return current; } -/* Initialize IGD OpRegion, called from ACPI code */ -static int update_igd_opregion(igd_opregion_t *opregion) -{ - /* FIXME: Add platform specific mailbox initialization */ - - return 0; -} - unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { @@ -480,19 +472,6 @@ current = acpi_align_current(current); } - if (CONFIG(INTEL_GMA_ADD_VBT)) { - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - intel_gma_init_igd_opregion(opregion); - if (gnvs) - gnvs->aslb = (u32)opregion; - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - } - ssdt2 = (acpi_header_t *)current; memset(ssdt2, 0, sizeof(acpi_header_t)); acpi_create_serialio_ssdt(ssdt2); diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 860f4d7..4f6ed90 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -56,48 +56,6 @@ TOLM, 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index d6671f6..a603268 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -61,20 +61,7 @@ /* Post VBIOS Init */ gfx_post_vbios_init(dev); } - intel_gma_restore_opregion(); -} - -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 32d6b8a..adefcda 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -49,40 +49,7 @@ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 unused[76]; /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index a28ef4b..aa3c344 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -46,48 +46,6 @@ PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dbb4205..79d0ae5 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -492,19 +492,6 @@ gtt_rmw(0x64810, 0xfffff800, dpdiv); } -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - static void igd_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); @@ -588,32 +575,7 @@ gfx_set_init_done(lightup_ok); } - intel_gma_restore_opregion(); -} - -static unsigned long -gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) -{ - igd_opregion_t *opregion = (igd_opregion_t *)current; - global_nvs_t *gnvs; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - /* GNVS has been already set up */ - gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - if (gnvs) { - /* IGD OpRegion Base Address */ - gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); - } else { - printk(BIOS_ERR, "Error: GNVS table not found.\n"); - } - - current = acpi_align_current(current); - return current; + intel_gma_init_igd_opregion(); } static void gma_generate_ssdt(struct device *dev) @@ -629,7 +591,6 @@ .enable_resources = &pci_dev_enable_resources, .init = &igd_init, .ops_pci = &broadwell_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, .acpi_fill_ssdt = gma_generate_ssdt, }; diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index b2bc97a..925a699 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -39,40 +39,7 @@ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd2; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused2[11]; + u8 unused2[76]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c index 84e9776..9046119 100644 --- a/src/soc/intel/cannonlake/graphics.c +++ b/src/soc/intel/cannonlake/graphics.c @@ -72,20 +72,6 @@ /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } -} -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 55c181b..0b2d635 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -132,7 +132,6 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = graphics_soc_write_acpi_opregion, .acpi_fill_ssdt = gma_generate_ssdt, #endif .scan_bus = scan_generic_bus, diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 5a68952..3af5728 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -19,20 +19,6 @@ */ void graphics_soc_init(struct device *dev); -/* - * Write ASL entry for Graphics opregion - * Input: - * struct device *device: device structure - * current: start address of graphics opregion - * rsdp: pointer to RSDT (and XSDT) structure - * - * Output: - * End address of graphics opregion so that the called - * can use the same for future calls to write_acpi_tables - */ -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp); - /* i915 controller info for ACPI backlight controls */ const struct i915_gpu_controller_info * intel_igd_get_controller_info(struct device *device); diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 0ee340c..ab2fc54 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -30,6 +30,11 @@ void graphics_soc_init(struct device *dev) { + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -39,30 +44,12 @@ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(RUN_FSP_GOP)) - return; + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/jasperlake/graphics.c b/src/soc/intel/jasperlake/graphics.c index 0ee340c..bd9f9d3 100644 --- a/src/soc/intel/jasperlake/graphics.c +++ b/src/soc/intel/jasperlake/graphics.c @@ -30,6 +30,11 @@ void graphics_soc_init(struct device *dev) { + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -39,30 +44,13 @@ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(RUN_FSP_GOP)) + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ return; + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 7c40630..85d8ff6 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -60,48 +60,6 @@ A4GB, 64, // 0x55 - 0x5C Base of above 4GB MMIO Resource A4GS, 64, // 0x5D - 0x64 Length of above 4GB MMIO Resource - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index c338a67..bc9a31b 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -125,55 +125,7 @@ pci_dev_init(dev); } - intel_gma_restore_opregion(); -} - -uintptr_t gma_get_gnvs_aslb(const void *gnvs) -{ - const global_nvs_t *gnvs_ptr = gnvs; - return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); -} - -void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) -{ - global_nvs_t *gnvs_ptr = gnvs; - if (gnvs_ptr) - gnvs_ptr->aslb = aslb; -} - -/* Initialize IGD OpRegion, called from ACPI code */ -static void update_igd_opregion(igd_opregion_t *opregion) -{ - /* FIXME: Add platform specific mailbox initialization */ -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - /* If GOP is not used, exit here */ - if (!CONFIG(INTEL_GMA_ADD_VBT)) - return current; - - /* If IGD is disabled, exit here */ - if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) - return current; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - if (gnvs) - gnvs->aslb = (u32)(uintptr_t)opregion; - update_igd_opregion(opregion); - current += sizeof(igd_opregion_t); - current = acpi_align_current(current); - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; + intel_gma_init_igd_opregion(); } const struct i915_gpu_controller_info * diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 480805b..8621106 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -49,42 +49,7 @@ u8 e4gm; /* 0x54 - Enable above 4GB MMIO Resource */ u64 a4gb; /* 0x55 - 0x5C Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x5D - 0x64 Length of above 4GB MMIO Resource */ - u8 rsvd[79]; - - /* IGD OpRegion */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - - u8 unused[11]; + u8 rsvd[155]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index 4054bd5..2164338 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -36,6 +36,11 @@ void graphics_soc_init(struct device *dev) { + /* IGD needs to Bus Master */ + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig @@ -45,30 +50,12 @@ * In case of non-FSP solution, SoC need to select VGA_ROM_RUN * Kconfig to perform GFX initialization through VGA OpRom. */ - if (CONFIG(RUN_FSP_GOP)) - return; + if (CONFIG(RUN_FSP_GOP)) { + /* nothing to do */ + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } - /* IGD needs to Bus Master */ - uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* Initialize PCI device, load/execute BIOS Option ROM */ - pci_dev_init(dev); -} - -uintptr_t graphics_soc_write_acpi_opregion(struct device *device, - uintptr_t current, struct acpi_rsdp *rsdp) -{ - igd_opregion_t *opregion; - - printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); - opregion = (igd_opregion_t *)current; - - if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) - return current; - - current += sizeof(igd_opregion_t); - - return acpi_align_current(current); + intel_gma_init_igd_opregion(); } diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 8e99d49..2d42107 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -109,47 +109,8 @@ /* XHCI */ Offset (0xb2), XHCI, 8, - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value /* ChromeOS specific */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 25c392d..8cb07b8 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -97,38 +97,7 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ + u8 rsvd12[65]; u8 tpiq; /* 0xf5 - trackpad IRQ value */ u8 rsvd13[10]; /* 0xf6 - rsvd */ diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index c556573..75e0d0d 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -91,27 +91,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index d71b1e0..4f3abeb 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -105,33 +105,6 @@ GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index 980ab0b..0ddaf07 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -90,27 +90,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 6778fe7..a9824d2 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -109,33 +109,6 @@ GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 0954daa..d1d3a73 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -92,27 +92,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index ce810eb..dbc23b4 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -109,33 +109,6 @@ GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 /* Mainboard Specific (TODO move elsewhere) */ Offset (0xf0), DOCK, 8, // 0xf0 - Docking Status diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 95bfa26..82b1b1e 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -90,27 +90,7 @@ u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; + u8 rsvd11[67]; /* Mainboard specific */ u8 dock; /* 0xf0 - Docking Status */ u8 bten; diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index c091b6f..bd02ec3 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -96,39 +96,7 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 rsvd13[76]; /* 0xf5 - rsvd */ /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ad7df7f..12e3950 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -104,48 +104,6 @@ Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer - /* IGD OpRegion */ - Offset (0xb4), - ASLB, 32, // 0xb4 - IGD OpRegion Base Address - IBTT, 8, // 0xb8 - IGD boot panel device - IPAT, 8, // 0xb9 - IGD panel type CMOS option - ITVF, 8, // 0xba - IGD TV format CMOS option - ITVM, 8, // 0xbb - IGD TV minor format option - IPSC, 8, // 0xbc - IGD panel scaling - IBLC, 8, // 0xbd - IGD BLC config - IBIA, 8, // 0xbe - IGD BIA config - ISSC, 8, // 0xbf - IGD SSC config - I409, 8, // 0xc0 - IGD 0409 modified settings - I509, 8, // 0xc1 - IGD 0509 modified settings - I609, 8, // 0xc2 - IGD 0609 modified settings - I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD Power conservation feature - IDMS, 8, // 0xc5 - IGD DVMT memory size - IF1E, 8, // 0xc6 - IGD function 1 enable - HVCO, 8, // 0xc7 - IGD HPLL VCO - NXD1, 32, // 0xc8 - IGD _DGS next DID1 - NXD2, 32, // 0xcc - IGD _DGS next DID2 - NXD3, 32, // 0xd0 - IGD _DGS next DID3 - NXD4, 32, // 0xd4 - IGD _DGS next DID4 - NXD5, 32, // 0xd8 - IGD _DGS next DID5 - NXD6, 32, // 0xdc - IGD _DGS next DID6 - NXD7, 32, // 0xe0 - IGD _DGS next DID7 - NXD8, 32, // 0xe4 - IGD _DGS next DID8 - - ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) - PAVP, 8, // 0xe9 - IGD PAVP data - Offset (0xeb), - OSCC, 8, // 0xeb - PCIe OSC control - NPCE, 8, // 0xec - native PCIe support - PLFL, 8, // 0xed - platform flavor - BREV, 8, // 0xee - board revision - DPBM, 8, // 0xef - digital port b mode - DPCM, 8, // 0xf0 - digital port c mode - DPDM, 8, // 0xf1 - digital port d mode - ALFP, 8, // 0xf2 - active lfp - IMON, 8, // 0xf3 - current graphics turbo imon value - MMIO, 8, // 0xf4 - 64bit mmio support - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index c35b4b5..ff0ea27 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -73,40 +73,7 @@ u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ - u8 rsvd6[16]; - /* IGD OpRegion (not implemented yet) */ - u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; /* 0xb8 - IGD boot type */ - u8 ipat; /* 0xb9 - IGD panel type */ - u8 itvf; /* 0xba - IGD TV format */ - u8 itvm; /* 0xbb - IGD TV minor format */ - u8 ipsc; /* 0xbc - IGD Panel Scaling */ - u8 iblc; /* 0xbd - IGD BLC configuration */ - u8 ibia; /* 0xbe - IGD BIA configuration */ - u8 issc; /* 0xbf - IGD SSC configuration */ - u8 i409; /* 0xc0 - IGD 0409 modified settings */ - u8 i509; /* 0xc1 - IGD 0509 modified settings */ - u8 i609; /* 0xc2 - IGD 0609 modified settings */ - u8 i709; /* 0xc3 - IGD 0709 modified settings */ - u8 idmm; /* 0xc4 - IGD Power Conservation */ - u8 idms; /* 0xc5 - IGD DVMT memory size */ - u8 if1e; /* 0xc6 - IGD Function 1 Enable */ - u8 hvco; /* 0xc7 - IGD HPLL VCO */ - u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ - u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ - u8 pavp; /* 0xe9 - IGD PAVP data */ - u8 rsvd12; /* 0xea - rsvd */ - u8 oscc; /* 0xeb - PCIe OSC control */ - u8 npce; /* 0xec - native PCIe support */ - u8 plfl; /* 0xed - platform flavor */ - u8 brev; /* 0xee - board revision */ - u8 dpbm; /* 0xef - digital port b mode */ - u8 dpcm; /* 0xf0 - digital port c mode */ - u8 dpdm; /* 0xf1 - digital port c mode */ - u8 alfp; /* 0xf2 - active lfp */ - u8 imon; /* 0xf3 - current graphics turbo imon value */ - u8 mmio; /* 0xf4 - 64bit mmio support */ - u8 rsvd13[11]; /* 0xf5 - rsvd */ + u8 rsvd6[92]; /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/c/coreboot/+/40724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Gerrit-Change-Number: 40724 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: arch/x86: Add option to compress postcar stage
by Arthur Heymans (Code Review) 10 May '23

10 May '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36674 ) Change subject: arch/x86: Add option to compress postcar stage ...................................................................... arch/x86: Add option to compress postcar stage The LZ4 decompressor was already linked in romstage. Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36674/1 diff --git a/src/Kconfig b/src/Kconfig index 0d56291..17bf545 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -158,6 +158,16 @@ that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI). +config COMPRESS_POSTCAR + bool "Compress postcar with LZ4" + depends on POSTCAR_STAGE + # Default value set at the end of the file + help + Compress postcar with LZ4 to save flash space and speed up boot, + since the time for reading the image from SPI (and in the vboot + case verifying it) is usually much greater than the time spent + decompressing. + config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) @@ -1203,6 +1213,9 @@ config COMPRESS_RAMSTAGE default y if !UNCOMPRESSED_RAMSTAGE +config COMPRESS_POSTCAR + default y + config COMPRESS_PRERAM_STAGES depends on !ARCH_X86 default y diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 447fd57..8c35176 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -278,11 +278,16 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ +CBFS_POSTCAR_COMPRESS_FLAG := none +ifeq ($(CONFIG_COMPRESS_POSTCAR),y) +CBFS_POSTCAR_COMPRESS_FLAG := lz4 +endif + # Add postcar to CBFS cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage -$(CONFIG_CBFS_PREFIX)/postcar-compression := none +$(CONFIG_CBFS_PREFIX)/postcar-compression := $(CBFS_POSTCAR_COMPRESS_FLAG) ############################################################################### # ramstage -- To view, visit https://review.coreboot.org/c/coreboot/+/36674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fdc6066027447bf72968c66e6f5eb5fbb630c7 Gerrit-Change-Number: 36674 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

10 24

Change in ...coreboot[master]: mb/lenovo/x60: Override default SPI OPs
by Arthur Heymans (Code Review) 10 May '23

10 May '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33041 Change subject: mb/lenovo/x60: Override default SPI OPs ...................................................................... mb/lenovo/x60: Override default SPI OPs The thinkpad X60 with SST flash needs different SPI OPs to make flashrom happy. flashrom uses AAI for writing. One potential issue is that fast_read is not possible anymore, but on x86 the flash is memory mapped so this won't matter. Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x60/mainboard.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33041/1 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 274a151..3aef020 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <spi_flash.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/device.h> @@ -26,6 +27,7 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> #include <arch/acpigen.h> +#include <southbridge/intel/common/spi.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT @@ -66,6 +68,28 @@ return ARRAY_SIZE(cst_entries); } + +static const struct intel_spi_config spi_config_sst = { + .opprefixes = {0x06, 0x50}, + .ops = {{0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ + {0x04, WRITE_NO_ADDR}} /* Write Disable */ +}; + +void intel_southbridge_override_spi(struct intel_spi_config *spi_config) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + + if (strcmp(flash->name, "SST25VF016B") == 0) { + memcpy(spi_config, &spi_config_sst, sizeof(spi_config_sst)); + } +} + static void mainboard_init(struct device *dev) { struct device *idedev, *sdhci_dev; -- To view, visit https://review.coreboot.org/c/coreboot/+/33041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id65fc632b33962bd505283c842c45feb85c75e5f Gerrit-Change-Number: 33041 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: ec/google/chromeec: Guard battery-related ACPI code
by Matt DeVillier (Code Review) 30 Apr '23

30 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48859 ) Change subject: ec/google/chromeec: Guard battery-related ACPI code ...................................................................... ec/google/chromeec: Guard battery-related ACPI code Boards which do not have a built-in battery, like Fizz and Puff-based Chromeboxes, still report the board using a battery but one not being connected, leading to a red battery icon with a disabled symbol in many OSes. Mitigate this by guarding the inclusion of battery.asl with ifndef EC_NO_BATTERY_PRESENT, and define this for Fizz and Puff-based boards. Also guard _Qxx methods which reference BAT0. Test: build/boot Puff variant, boot OS (eg, Windows 10 2H20), check that a missing battery is not reported by the OS. Change-Id: I41df5a925c9a15553d9e818a2efed2210311fd45 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48859/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b..effc2bf 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -263,20 +263,25 @@ // Battery Low Event Method (_Q06, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY LOW", Debug) Notify (BAT0, 0x80) +#endif } // Battery Critical Event Method (_Q07, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY CRITICAL", Debug) Notify (BAT0, 0x80) +#endif } // Battery Info Event Method (_Q08, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY INFO", Debug) Notify (BAT0, 0x81) #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE @@ -284,6 +289,7 @@ Notify (BAT1, 0x81) } #endif +#endif } // Thermal Overload Event @@ -323,8 +329,10 @@ // Battery Shutdown Imminent Method (_Q11, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY SHUTDOWN", Debug) Notify (BAT0, 0x80) +#endif } // Throttle Start @@ -357,6 +365,7 @@ // Battery Status Method (_Q17, 0, NotSerialized) { +#ifndef EC_NO_BATTERY_PRESENT Store ("EC: BATTERY STATUS", Debug) Notify (BAT0, 0x80) #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE @@ -364,6 +373,7 @@ Notify (BAT1, 0x80) } #endif +#endif } // MKBP interrupt. @@ -567,7 +577,9 @@ #endif #include "ac.asl" +#ifndef EC_NO_BATTERY_PRESENT #include "battery.asl" +#endif #include "cros_ec.asl" #ifdef EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h index 504b6de..b02a389 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h @@ -53,4 +53,7 @@ #define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ +/* Fizz-based boards do not have a built-in battery */ +#define EC_NO_BATTERY_PRESENT + #endif diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h index 986cf61..36e1b73 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/puff/ec.h @@ -56,4 +56,7 @@ /* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ #define EC_ENABLE_SYNC_IRQ +/* Puff-based boards do not have a built-in battery */ +#define EC_NO_BATTERY_PRESENT + #endif /* __BASEBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41df5a925c9a15553d9e818a2efed2210311fd45 Gerrit-Change-Number: 48859 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: arch/x86/include/arch/pci_io_cfg.h: Fix UndefinedBehavior sanitizer c...
by Shawn C (Code Review) 10 Apr '23

10 Apr '23

Shawn C has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49076 ) Change subject: arch/x86/include/arch/pci_io_cfg.h: Fix UndefinedBehavior sanitizer complain ...................................................................... arch/x86/include/arch/pci_io_cfg.h: Fix UndefinedBehavior sanitizer complain GCC build option "-fsanitize=shift" will complain: "runtime error: left shift of 1 by 31 places cannot be represented in type 'int'" Signed-off-by: Shawn C <citypw(a)hardenedlinux.org> Change-Id: I6eeee1e92b616f68aa60eb74771912dd00ff7712 --- M src/arch/x86/include/arch/pci_io_cfg.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/49076/1 diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 61dd106..5e9761e 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -10,7 +10,7 @@ static __always_inline uint32_t pci_io_encode_addr(pci_devfn_t dev, uint16_t reg) { - uint32_t addr = 1 << 31; + uint32_t addr = 1UL << 31; addr |= dev >> 4; addr |= reg & 0xfc; -- To view, visit https://review.coreboot.org/c/coreboot/+/49076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6eeee1e92b616f68aa60eb74771912dd00ff7712 Gerrit-Change-Number: 49076 Gerrit-PatchSet: 1 Gerrit-Owner: Shawn C <citypw(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: mb/apple: Add MacBook Air 5,2 (A1466)
by Evgeny Zinoviev (Code Review) 08 Apr '23

08 Apr '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32604 Change subject: mb/apple: Add MacBook Air 5,2 (A1466) ...................................................................... mb/apple: Add MacBook Air 5,2 (A1466) This is WIP. Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/mainboard/apple/macbookair5_2/Kconfig A src/mainboard/apple/macbookair5_2/Kconfig.name A src/mainboard/apple/macbookair5_2/Makefile.inc A src/mainboard/apple/macbookair5_2/acpi/ec.asl A src/mainboard/apple/macbookair5_2/acpi/platform.asl A src/mainboard/apple/macbookair5_2/acpi/superio.asl A src/mainboard/apple/macbookair5_2/acpi_tables.c A src/mainboard/apple/macbookair5_2/board_info.txt A src/mainboard/apple/macbookair5_2/devicetree.cb A src/mainboard/apple/macbookair5_2/dsdt.asl A src/mainboard/apple/macbookair5_2/gma-mainboard.ads A src/mainboard/apple/macbookair5_2/gnvs.c A src/mainboard/apple/macbookair5_2/gpio.c A src/mainboard/apple/macbookair5_2/hda_verb.c A src/mainboard/apple/macbookair5_2/mainboard.c A src/mainboard/apple/macbookair5_2/romstage.c A src/mainboard/apple/macbookair5_2/spd.bin 17 files changed, 843 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32604/1 diff --git a/src/mainboard/apple/macbookair5_2/Kconfig b/src/mainboard/apple/macbookair5_2/Kconfig new file mode 100644 index 0000000..853021f --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Kconfig @@ -0,0 +1,55 @@ +if BOARD_APPLE_MACBOOKAIR5_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookair5_2 + +config MAINBOARD_PART_NUMBER + string + default "MacBookAir5,2" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x7270 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "Apple Inc." + +endif diff --git a/src/mainboard/apple/macbookair5_2/Kconfig.name b/src/mainboard/apple/macbookair5_2/Kconfig.name new file mode 100644 index 0000000..d8a1fbf --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKAIR5_2 + bool "MacBookAir5,2" diff --git a/src/mainboard/apple/macbookair5_2/Makefile.inc b/src/mainboard/apple/macbookair5_2/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookair5_2/acpi/ec.asl b/src/mainboard/apple/macbookair5_2/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookair5_2/acpi/platform.asl b/src/mainboard/apple/macbookair5_2/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookair5_2/acpi/superio.asl b/src/mainboard/apple/macbookair5_2/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi/superio.asl diff --git a/src/mainboard/apple/macbookair5_2/acpi_tables.c b/src/mainboard/apple/macbookair5_2/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookair5_2/board_info.txt b/src/mainboard/apple/macbookair5_2/board_info.txt new file mode 100644 index 0000000..cbd72ee --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: WSON-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookair5_2/devicetree.cb b/src/mainboard/apple/macbookair5_2/devicetree.cb new file mode 100644 index 0000000..efc5ddb --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/devicetree.cb @@ -0,0 +1,119 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "2" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000710" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "10" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "740" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x07100710" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x8086 0x7270 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00fe + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00fe + end + end +end diff --git a/src/mainboard/apple/macbookair5_2/dsdt.asl b/src/mainboard/apple/macbookair5_2/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookair5_2/gma-mainboard.ads b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookair5_2/gnvs.c b/src/mainboard/apple/macbookair5_2/gnvs.c new file mode 100644 index 0000000..def9e5f --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gnvs.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* the lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookair5_2/gpio.c b/src/mainboard/apple/macbookair5_2/gpio.c new file mode 100644 index 0000000..9f2cd14 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/gpio.c @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookair5_2/hda_verb.c b/src/mainboard/apple/macbookair5_2/hda_verb.c new file mode 100644 index 0000000..6c8e555 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b5600, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b5600), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x0e2b4030), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x400000f0), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x400000f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookair5_2/mainboard.c b/src/mainboard/apple/macbookair5_2/mainboard.c new file mode 100644 index 0000000..d497c51 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/mainboard.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ +// { +// int i; +// const u8 dmp[256] = { +// /* 00 */ 0x40, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 10 */ 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 20 */ 0x00, 0x80, 0x16, 0x16, 0xe0, 0x40, 0x4f, 0x4e, 0x7a, 0x34, 0x35, 0x31, 0x38, 0x31, 0x32, 0x44, +// /* 30 */ 0x4b, 0x52, 0x4e, 0x41, 0x38, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42, +// /* 40 */ 0x43, 0x44, 0x45, 0x00, 0x02, 0x14, 0x11, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 60 */ 0x03, 0x00, 0x00, 0x00, 0x0f, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +// }; +// +// printk(BIOS_DEBUG, "Replaying EC dump ..."); +// for (i = 0; i < 256; i++) +// ec_write (i, dmp[i]); +// printk(BIOS_DEBUG, "done\n"); +// } + + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + +// /* FIXME: fix those values*/ +// install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, +// GMA_INT15_PANEL_FIT_DEFAULT, +// GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookair5_2/romstage.c b/src/mainboard/apple/macbookair5_2/romstage.c new file mode 100644 index 0000000..6594b15 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x00000401); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); +} + +void mainboard_rcba_config(void) +{ + RCBA32(0x3414) = 0x00000020; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 512) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file + 256, 128); + } +} diff --git a/src/mainboard/apple/macbookair5_2/spd.bin b/src/mainboard/apple/macbookair5_2/spd.bin new file mode 100644 index 0000000..2e2a6b4 --- /dev/null +++ b/src/mainboard/apple/macbookair5_2/spd.bin Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/32604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ebe6f87a8254871698be74f913b9d969d722447 Gerrit-Change-Number: 32604 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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