August 2022 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: lib: Rename edid_fill_fb.c
by Patrick Rudolph (Code Review) Aug. 7, 2023

Aug. 7, 2023

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39431 ) Change subject: lib: Rename edid_fill_fb.c ...................................................................... lib: Rename edid_fill_fb.c Rename edid_fill_fb.c to framebuffer_info.c as it doesn't deal with EDID that much any more. Change-Id: Ic7eb6432eee9808aaa9a48e6bcd61bf136a8b938 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/Makefile.inc R src/lib/framebuffer_info.c 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39431/1 diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a1fb8c2..76ace63 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -134,7 +134,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c -ramstage-y += edid_fill_fb.c +ramstage-y += framebuffer_info.c ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c diff --git a/src/lib/edid_fill_fb.c b/src/lib/framebuffer_info.c similarity index 100% rename from src/lib/edid_fill_fb.c rename to src/lib/framebuffer_info.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7eb6432eee9808aaa9a48e6bcd61bf136a8b938 Gerrit-Change-Number: 39431 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [HACK] Add soc/broadwell based hp/folio_9480m code
by Iru Cai (vimacs) (Code Review) Aug. 7, 2023

Aug. 7, 2023

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47345 to review the following change. Change subject: [HACK] Add soc/broadwell based hp/folio_9480m code ...................................................................... [HACK] Add soc/broadwell based hp/folio_9480m code The laptop still boots with this code. Change-Id: I0d74c59ff8e8f32f49627fb7edc270887ebd5339 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A src/mainboard/hp/folio_9480m_bdw/Kconfig A src/mainboard/hp/folio_9480m_bdw/Kconfig.name A src/mainboard/hp/folio_9480m_bdw/Makefile.inc A src/mainboard/hp/folio_9480m_bdw/acpi/ec.asl A src/mainboard/hp/folio_9480m_bdw/acpi/platform.asl A src/mainboard/hp/folio_9480m_bdw/acpi/superio.asl A src/mainboard/hp/folio_9480m_bdw/acpi_tables.c A src/mainboard/hp/folio_9480m_bdw/board_info.txt A src/mainboard/hp/folio_9480m_bdw/data.vbt A src/mainboard/hp/folio_9480m_bdw/devicetree.cb A src/mainboard/hp/folio_9480m_bdw/dsdt.asl A src/mainboard/hp/folio_9480m_bdw/gma-mainboard.ads A src/mainboard/hp/folio_9480m_bdw/gpio.c A src/mainboard/hp/folio_9480m_bdw/hda_verb.c A src/mainboard/hp/folio_9480m_bdw/pei_data.c A src/mainboard/hp/folio_9480m_bdw/romstage.c 16 files changed, 455 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47345/1 diff --git a/src/mainboard/hp/folio_9480m_bdw/Kconfig b/src/mainboard/hp/folio_9480m_bdw/Kconfig new file mode 100644 index 0000000..2858d97 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/Kconfig @@ -0,0 +1,48 @@ +if BOARD_HP_FOLIO_9480M_BDW + +config BOARD_SPECIFIC_OPTIONS + def_bool y + # The board has a 16MB flash, but the end of the flash needs + # to be reserved, so we use 12MB as default + select BOARD_ROMSIZE_KB_12288 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select SERIRQ_CONTINUOUS_MODE + select SOC_INTEL_BROADWELL + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/folio_9480m_bdw" + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook Folio 9480m" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +config EC_HP_KBC1126_GPE + hex + default 0x6 + +config MAX_CPUS + int + default 4 + +endif diff --git a/src/mainboard/hp/folio_9480m_bdw/Kconfig.name b/src/mainboard/hp/folio_9480m_bdw/Kconfig.name new file mode 100644 index 0000000..922552b --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_FOLIO_9480M_BDW + bool "EliteBook Folio 9480m (using Broadwell SoC code)" diff --git a/src/mainboard/hp/folio_9480m_bdw/Makefile.inc b/src/mainboard/hp/folio_9480m_bdw/Makefile.inc new file mode 100644 index 0000000..2543ee7 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += gpio.c +romstage-y += pei_data.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += pei_data.c diff --git a/src/mainboard/hp/folio_9480m_bdw/acpi/ec.asl b/src/mainboard/hp/folio_9480m_bdw/acpi/ec.asl new file mode 100644 index 0000000..baa17a4 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/folio_9480m_bdw/acpi/platform.asl b/src/mainboard/hp/folio_9480m_bdw/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/folio_9480m_bdw/acpi/superio.asl b/src/mainboard/hp/folio_9480m_bdw/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/folio_9480m_bdw/acpi_tables.c b/src/mainboard/hp/folio_9480m_bdw/acpi_tables.c new file mode 100644 index 0000000..ca6f64b --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/acpi_tables.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/hp/folio_9480m_bdw/board_info.txt b/src/mainboard/hp/folio_9480m_bdw/board_info.txt new file mode 100644 index 0000000..fdd0d60 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7… +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/hp/folio_9480m_bdw/data.vbt b/src/mainboard/hp/folio_9480m_bdw/data.vbt new file mode 100644 index 0000000..1a62a07 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/data.vbt Binary files differ diff --git a/src/mainboard/hp/folio_9480m_bdw/devicetree.cb b/src/mainboard/hp/folio_9480m_bdw/devicetree.cb new file mode 100644 index 0000000..02ba69f --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/devicetree.cb @@ -0,0 +1,72 @@ +chip soc/intel/broadwell + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0x0 on + subsystemid 0x103c 0x22da inherit + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip soc/intel/broadwell/pch + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "sata_port1_gen3_dtle" = "0x6" + # SATA(1), M.2(3) + register "sata_port_map" = "0xa" + device pci 13.0 off end # Intel Smart Sound DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2 2230" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + # This laptop uses MEC1322, but it has the same interface + # as the KBC1126 laptops + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/folio_9480m_bdw/dsdt.asl b/src/mainboard/hp/folio_9480m_bdw/dsdt.asl new file mode 100644 index 0000000..895d639 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <soc/intel/broadwell/acpi/platform.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> + } + + /* FIXME: We cannot override the default _WAK and _PTS in soc/broadwell */ + /* #include "acpi/platform.asl" */ +} diff --git a/src/mainboard/hp/folio_9480m_bdw/gma-mainboard.ads b/src/mainboard/hp/folio_9480m_bdw/gma-mainboard.ads new file mode 100644 index 0000000..85e9ded --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DP1/HDMI1: DisplayPorts on board and dock + HDMI1, + DP2, -- DP2: VGA ports on board and dock + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/folio_9480m_bdw/gpio.c b/src/mainboard/hp/folio_9480m_bdw/gpio.c new file mode 100644 index 0000000..d08713c --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> + +const struct gpio_config mainboard_gpio_config[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = PCH_GPIO_OUT_LOW, + [3] = PCH_GPIO_OUT_HIGH, + [4] = PCH_GPIO_OUT_HIGH, + [5] = PCH_GPIO_OUT_HIGH, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = PCH_GPIO_OUT_HIGH, + [9] = PCH_GPIO_OUT_HIGH, + [10] = PCH_GPIO_OUT_HIGH, + [11] = PCH_GPIO_OUT_HIGH, + [12] = PCH_GPIO_NATIVE, + [13] = PCH_GPIO_OUT_HIGH, + [14] = PCH_GPIO_OUT_HIGH, + [15] = PCH_GPIO_OUT_HIGH, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = PCH_GPIO_OUT_HIGH, + [19] = PCH_GPIO_NATIVE, + [20] = PCH_GPIO_NATIVE, + [21] = PCH_GPIO_NATIVE, + [22] = PCH_GPIO_OUT_HIGH, + [23] = PCH_GPIO_OUT_HIGH, + [24] = PCH_GPIO_OUT_HIGH, + [25] = PCH_GPIO_OUT_HIGH, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = PCH_GPIO_OUT_HIGH, + [29] = PCH_GPIO_OUT_HIGH, + [30] = PCH_GPIO_NATIVE, + [31] = PCH_GPIO_NATIVE, + [32] = PCH_GPIO_NATIVE, + [33] = PCH_GPIO_NATIVE, + [34] = PCH_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = PCH_GPIO_NATIVE, + [38] = PCH_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = PCH_GPIO_OUT_HIGH, + [44] = PCH_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = PCH_GPIO_OUT_HIGH, + [48] = PCH_GPIO_OUT_LOW, + [49] = PCH_GPIO_OUT_HIGH, + [50] = PCH_GPIO_OUT_HIGH, + [51] = PCH_GPIO_OUT_HIGH, + [52] = PCH_GPIO_OUT_HIGH, + [53] = PCH_GPIO_OUT_HIGH, + [54] = PCH_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = PCH_GPIO_OUT_HIGH, + [57] = PCH_GPIO_OUT_LOW, + [58] = PCH_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = PCH_GPIO_OUT_HIGH, + [61] = PCH_GPIO_OUT_LOW, + [62] = PCH_GPIO_NATIVE, + [63] = PCH_GPIO_NATIVE, + [64] = PCH_GPIO_OUT_HIGH, + [65] = PCH_GPIO_OUT_LOW, + [66] = PCH_GPIO_OUT_HIGH, + [67] = PCH_GPIO_OUT_HIGH, + [68] = PCH_GPIO_OUT_HIGH, + [69] = PCH_GPIO_OUT_HIGH, + [70] = PCH_GPIO_OUT_LOW, + [71] = PCH_GPIO_NATIVE, + [72] = PCH_GPIO_NATIVE, + [73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [74] = PCH_GPIO_NATIVE, + [75] = PCH_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = PCH_GPIO_OUT_LOW, + [81] = PCH_GPIO_NATIVE, + [82] = PCH_GPIO_OUT_HIGH, + [83] = PCH_GPIO_OUT_HIGH, + [84] = PCH_GPIO_OUT_HIGH, + [85] = PCH_GPIO_OUT_HIGH, + [86] = PCH_GPIO_OUT_HIGH, + [87] = PCH_GPIO_OUT_HIGH, + [88] = PCH_GPIO_OUT_HIGH, + [89] = PCH_GPIO_OUT_HIGH, + [90] = PCH_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = PCH_GPIO_OUT_HIGH, + PCH_GPIO_END +}; diff --git a/src/mainboard/hp/folio_9480m_bdw/hda_verb.c b/src/mainboard/hp/folio_9480m_bdw/hda_verb.c new file mode 100644 index 0000000..9ee6de0 --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/hda_verb.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c22db, /* Subsystem ID */ + 57, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c22db), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* The following is from the OEM firmware */ + 0x02050007, 0x0204c200, 0x02050063, 0x02044800, + 0x02050066, 0x02040809, 0x02050015, 0x02048842, + 0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd, + 0x02050065, 0x02042000, 0x0205001c, 0x0204c900, + 0x02050018, 0x02043788, 0x02050008, 0x02048210, + 0x02050068, 0x02043022, 0x02050006, 0x02040800, + 0x02050061, 0x02040403, 0x02050061, 0x02040403, + 0x0205005f, 0x02040800, 0x02050060, 0x02040800, + 0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4, + 0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8, + 0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad, + 0x02050036, 0x0204cbd2, 0x02050037, 0x02041605, + 0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f, + 0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54, + 0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000, + 0x02050030, 0x02041f5c, 0x02050031, 0x02040111, + 0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9, + 0x0205002f, 0x02040000, 0x02050042, 0x0204c66e, + 0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad, + 0x02050044, 0x0204ccdd, 0x02050045, 0x02041549, + 0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79, + 0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54, + 0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000, + 0x0205003f, 0x02041f4d, 0x02050040, 0x02040129, + 0x02050041, 0x02041f51, 0x02050049, 0x02041f61, + 0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4, + 0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad, + 0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98, + 0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e, + 0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54, + 0x02050053, 0x02040b73, 0x0205003d, 0x02040000, + 0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a, + 0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0, + 0x0205002f, 0x02040000, 0x02050058, 0x0204c17a, + 0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad, + 0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e, + 0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899, + 0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54, + 0x0205005e, 0x02041444, 0x0205003d, 0x02040000, + 0x02050055, 0x02041fd8, 0x02050056, 0x02040045, + 0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2, + 0x02050026, 0x02042828, 0x02050029, 0x02040250, + 0x02050004, 0x0204c09e, 0x0205000e, 0x02045001, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/folio_9480m_bdw/pei_data.c b/src/mainboard/hp/folio_9480m_bdw/pei_data.c new file mode 100644 index 0000000..9d2659c --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/pei_data.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[2] = 0xa4; + pei_data->dq_pins_interleaved = 1; + + pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 4, 0x0110, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 5, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/hp/folio_9480m_bdw/romstage.c b/src/mainboard/hp/folio_9480m_bdw/romstage.c new file mode 100644 index 0000000..8fc2f9e --- /dev/null +++ b/src/mainboard/hp/folio_9480m_bdw/romstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> + +void mainboard_pre_raminit(struct romstage_params *rp) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(&rp->pei_data); +} + +void mainboard_post_raminit(struct romstage_params *rp) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d74c59ff8e8f32f49627fb7edc270887ebd5339 Gerrit-Change-Number: 47345 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Zotac AD04: Review session / comments from 2020-11-10
by Name of user not set (Code Review) Aug. 7, 2023

Aug. 7, 2023

Name of user not set #1003174 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47723 ) Change subject: Zotac AD04: Review session / comments from 2020-11-10 ...................................................................... Zotac AD04: Review session / comments from 2020-11-10 Signed-off-by: moscovium-115 <3134c487(a)tutanota.com> Change-Id: I65b3438def4b98609e6dabf588677a7214252b7b --- M src/mainboard/zotac/ad04/BiosCallOuts.c M src/mainboard/zotac/ad04/Kconfig M src/mainboard/zotac/ad04/mainboard.c M src/mainboard/zotac/ad04/romstage.c D src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex D src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex 6 files changed, 23 insertions(+), 602 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47723/1 diff --git a/src/mainboard/zotac/ad04/BiosCallOuts.c b/src/mainboard/zotac/ad04/BiosCallOuts.c index 4944a85..8c62094 100644 --- a/src/mainboard/zotac/ad04/BiosCallOuts.c +++ b/src/mainboard/zotac/ad04/BiosCallOuts.c @@ -9,12 +9,11 @@ #include "gpio_ftns.h" static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr); -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, board_ReadSpd_from_cbfs }, + {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -26,33 +25,10 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /* Call the host environment interface to provide a user hook opportunity. */ -static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; return AGESA_SUCCESS; } - -static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) -{ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - - if (!ENV_ROMSTAGE) - return AGESA_UNSUPPORTED; - - u8 index = get_spd_offset(); - - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) - die("No SPD data\n"); - - return AGESA_SUCCESS; -} diff --git a/src/mainboard/zotac/ad04/Kconfig b/src/mainboard/zotac/ad04/Kconfig index 4dbf869..4f0f5a3 100644 --- a/src/mainboard/zotac/ad04/Kconfig +++ b/src/mainboard/zotac/ad04/Kconfig @@ -17,7 +17,6 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_SPD_IN_CBFS select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS - select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string @@ -25,7 +24,7 @@ config MAINBOARD_PART_NUMBER string - default "apu1" + default "ad04" config HW_MEM_HOLE_SIZEK hex @@ -60,42 +59,6 @@ bool default n -choice - prompt "J19 pins 1-10" - default APU1_PINMUX_OFF_C - -config APU1_PINMUX_OFF_C - bool "disable" - -config APU1_PINMUX_GPIO0 - bool "GPIO" - -config APU1_PINMUX_UART_C - bool "UART 0x3e8" - -endchoice - -config UART_C_RS485 - bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C - -choice - prompt "J19 pins 11-20" - default APU1_PINMUX_OFF_D - -config APU1_PINMUX_OFF_D - bool "disable" - -config APU1_PINMUX_GPIO1 - bool "GPIO" - -config APU1_PINMUX_UART_D - bool "UART 0x2e8" - -endchoice - -config UART_D_RS485 - bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D - config DIMM_SPD_SIZE int default 128 diff --git a/src/mainboard/zotac/ad04/mainboard.c b/src/mainboard/zotac/ad04/mainboard.c index 2562765..11228af 100644 --- a/src/mainboard/zotac/ad04/mainboard.c +++ b/src/mainboard/zotac/ad04/mainboard.c @@ -121,53 +121,6 @@ */ #define SIO_PORT 0x2e -/* -static void config_gpio_mux(void) -{ - struct device *uart, *gpio; - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); - gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0); - if (uart) - uart->enabled = CONFIG(APU1_PINMUX_UART_C); - if (gpio) - gpio->enabled = CONFIG(APU1_PINMUX_GPIO0); - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); - gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1); - if (uart) - uart->enabled = CONFIG(APU1_PINMUX_UART_D); - if (gpio) - gpio->enabled = CONFIG(APU1_PINMUX_GPIO1); -} -*/ - -/* -static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) -{ - struct resource *res; - res = new_resource(dev, reg); - res->base = val; - res->size = 0; - res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; -} -*/ - -/* -static void config_addon_uart(void) -{ - struct device *uart; - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); - if (uart && uart->enabled && CONFIG(UART_C_RS485)) - pnp_raw_resource(uart, 0xf2, 0x12); - - uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); - if (uart && uart->enabled && CONFIG(UART_D_RS485)) - pnp_raw_resource(uart, 0xf2, 0x12); -} -*/ - /********************************************** * Enable the dedicated functions of the board. **********************************************/ @@ -181,7 +134,7 @@ t = (struct smbios_type16 *)*current; len = sizeof(struct smbios_type16); memset(t, 0, len); - max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */ + max_capacity = 8; // From dmidecode.log t->type = SMBIOS_PHYS_MEMORY_ARRAY; t->handle = *handle; @@ -376,9 +329,9 @@ * LED2/D6/GPIO_190 should be 1 * LED3/D5/GPIO_191 should be 1 */ - configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); - configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); + /* configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */ + /* configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */ + /* configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */ usb_oc_setup(); } diff --git a/src/mainboard/zotac/ad04/romstage.c b/src/mainboard/zotac/ad04/romstage.c index f594827..0c959a2 100644 --- a/src/mainboard/zotac/ad04/romstage.c +++ b/src/mainboard/zotac/ad04/romstage.c @@ -17,23 +17,23 @@ bdata |= 0x05; //set bits 0,2 pm_write8(SB_PMIOA_REG5B, bdata); - /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */ - bdata = pm_read8(SB_PMIOA_REGEA); - bdata &= 0xfe; //clear bit 0 - bdata |= 0x01; //set bit 0 - pm_write8(SB_PMIOA_REGEA, bdata); + /* /1* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins *1/ */ + /* bdata = pm_read8(SB_PMIOA_REGEA); */ + /* bdata &= 0xfe; //clear bit 0 */ + /* bdata |= 0x01; //set bit 0 */ + /* pm_write8(SB_PMIOA_REGEA, bdata); */ - //configure required GPIOs - configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); - configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT); - configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); - configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); - configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); + /* //configure required GPIOs */ + /* configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */ + /* configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */ + /* configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT); */ + /* configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT); */ + /* configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT); */ + /* configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT); */ + /* configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT); */ + /* configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */ + /* configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */ + /* configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */ } void board_BeforeAgesa(struct sysinfo *cb) diff --git a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex deleted file mode 100644 index 72377c4..0000000 --- a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex +++ /dev/null @@ -1,234 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -# HYNIX-H5TQ2G83CFR - -# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -03 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[7:6]: reserved -19 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 1 = 8 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -01 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x01 divisor -# bits[7:4]: 0x01 dividend -# 1 / 1 = 1.0 ps -11 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0c = tCKmin of 1.5 ns = in multiples of MTB -0C - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -7E 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.5ns - DDR3-1333 -6C - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x30 = 6ns -30 - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x120 = 36ns - DDR3-1333 (see byte 21) -20 - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x28C = 49.5ns - DDR3-1333 -8C - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -00 05 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x00F0 = 30ns - DDR3-1333, 1 KB page size -00 F0 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 2 = Signal Loading -# bits[3:2]: reserved -# bits[6:4]: 4 = Die count -# bit7 : 0 = Standard Monolithic DRAM Device -42 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 (reserved) -00 - -# 40 - 47 (reserved) -00 00 00 00 00 00 00 00 - -# 48 - 55 (reserved) -00 00 00 00 00 00 00 00 - -# 56 - 59 (reserved) -00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 71 (reserved) -00 00 00 00 00 00 00 00 - -# 72 - 79 (reserved) -00 00 00 00 00 00 00 00 - -# 80 - 87 (reserved) -00 00 00 00 00 00 00 00 - -# 88 - 95 (reserved) -00 00 00 00 00 00 00 00 - -# 96 - 103 (reserved) -00 00 00 00 00 00 00 00 - -# 104 - 111 (reserved) -00 00 00 00 00 00 00 00 - -# 112 - 116 (reserved) -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -00 - -# 120 Module ID: Module Manufacture Year in BCD -# 0x13 = 2013 -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -13 12 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -c4 1b diff --git a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex deleted file mode 100644 index b6d24b4..0000000 --- a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex +++ /dev/null @@ -1,237 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -# HYNIX-H5TQ4G83MFR - -# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down -# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage -# bits[3:0]: 1 = 128 SPD Bytes Used -# bits[6:4]: 1 = 256 SPD Bytes Total -# bit7 : 0 = CRC covers bytes 0 ~ 125 -11 - -# 1 SPD Revision - -# 0x10 = Revision 1.0 -10 -# 2 Key Byte / DRAM Device Type -# bits[7:0]: 0x0b = DDR3 SDRAM -0B - -# 3 Key Byte / Module Type -# bits[3:0]: 3 = SO-DIMM -# bits[7:4]: reserved -03 - -# 4 SDRAM CHIP Density and Banks -# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip -# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip -# bits[6:4]: 0 = 3 (8 banks) -# bit7 : reserved -04 - -# 5 SDRAM Addressing -# bits[2:0]: 1 = 10 Column Address Bits -# bits[5:3]: 3 = 15 Row Address Bits -# bits[5:3]: 4 = 16 Row Address Bits -# bits[7:6]: reserved -21 - -# 6 Module Nominal Voltage, VDD -# bit0 : 0 = 1.5 V operable -# bit1 : 0 = NOT 1.35 V operable -# bit2 : 0 = NOT 1.25 V operable -# bits[7:3]: reserved -00 - -# 7 Module Organization -# bits[2:0]: 1 = 8 bits -# bits[5:3]: 0 = 1 Rank -# bits[7:6]: reserved -01 - -# 8 Module Memory Bus Width -# bits[2:0]: 3 = Primary bus width is 64 bits -# bits[4:3]: 0 = 0 bits (no bus width extension) -# bits[7:5]: reserved -03 - -# 9 Fine Timebase (FTB) Dividend / Divisor -# bits[3:0]: 0x01 divisor -# bits[7:4]: 0x01 dividend -# 1 / 1 = 1.0 ps -11 - -# 10 Medium Timebase (MTB) Dividend -# 11 Medium Timebase (MTB) Divisor -# 1 / 8 = .125 ns -01 08 - -# 12 SDRAM Minimum Cycle Time (tCKmin) -# 0x0c = tCKmin of 1.5 ns = in multiples of MTB -0C - -# 13 Reserved -00 - -# 14 CAS Latencies Supported, Least Significant Byte -# 15 CAS Latencies Supported, Most Significant Byte -# Cas Latencies of 11 - 5 are supported -7E 00 - -# 16 Minimum CAS Latency Time (tAAmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 17 Minimum Write Recovery Time (tWRmin) -# 0x78 = tWR of 15ns - All DDR3 speed grades -78 - -# 18 Minimum RAS# to CAS# Delay Time (tRCDmin) -# 0x6E = 13.5ns - DDR3-1333 -6C - -# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) -# 0x30 = 6ns -30 - -# 20 Minimum Row Precharge Delay Time (tRPmin) -# 0x6C = 13.5ns - DDR3-1333 -6C - -# 21 Upper Nibbles for tRAS and tRC -# bits[3:0]: tRAS most significant nibble = 1 (see byte 22) -# bits[7:4]: tRC most significant nibble = 1 (see byte 23) -11 - -# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB -# 0x120 = 36ns - DDR3-1333 (see byte 21) -20 - -# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB -# 0x28C = 49.5ns - DDR3-1333 -8C - -# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB -# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB -# 0x500 = 160ns - for 2 Gigabit chips -# 0x820 = 260ns - for 4 Gigabit chips -20 08 - -# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) -# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -3C - -# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) -# 0x3c = 7.5ns - All DDR3 SDRAM speed bins -3C - -# 28 Upper Nibble for tFAWmin -# 29 Minimum Four Activate Window Delay Time (tFAWmin) -# 0x00F0 = 30ns - DDR3-1333, 1 KB page size -00 F0 - -# 30 SDRAM Optional Feature -# bit0 : 1= RZQ/6 supported -# bit1 : 1 = RZQ/7 supported -# bits[6:2]: reserved -# bit7 : 1 = DLL Off mode supported -83 - -# 31 SDRAM Thermal and Refresh Options -# bit0 : 1 = Temp up to 95c supported -# bit1 : 0 = 85-95c uses 2x refresh rate -# bit2 : 1 = Auto Self Refresh supported -# bit3 : 0 = no on die thermal sensor -# bits[6:4]: reserved -# bit7 : 0 = partial self refresh supported -05 - -# 32 Module Thermal Sensor -# 0 = Thermal sensor not incorporated onto this assembly -00 - -# 33 SDRAM Device Type -# bits[1:0]: 2 = Signal Loading -# bits[3:2]: reserved -# bits[6:4]: 4 = Die count -# bit7 : 0 = Standard Monolithic DRAM Device -42 - -# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) -# 35 Fine Offset for Minimum CAS Latency Time (tAAmin) -# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) -# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin) -# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin) -00 00 00 00 00 - -# 39 (reserved) -00 - -# 40 - 47 (reserved) -00 00 00 00 00 00 00 00 - -# 48 - 55 (reserved) -00 00 00 00 00 00 00 00 - -# 56 - 59 (reserved) -00 00 00 00 - -# 60 Raw Card Extension, Module Nominal Height -# bits[4:0]: 0 = <= 15mm tall -# bits[7:5]: 0 = raw card revision 0-3 -00 - -# 61 Module Maximum Thickness -# bits[3:0]: 0 = thickness front <= 1mm -# bits[7:4]: 0 = thinkness back <= 1mm -00 - -# 62 Reference Raw Card Used -# bits[4:0]: 0 = Reference Raw card A used -# bits[6:5]: 0 = revision 0 -# bit7 : 0 = Reference raw cards A through AL -00 - -# 63 Address Mapping from Edge Connector to DRAM -# bit0 : 0 = standard mapping (not mirrored) -# bits[7:1]: reserved -00 - -# 64 - 71 (reserved) -00 00 00 00 00 00 00 00 - -# 72 - 79 (reserved) -00 00 00 00 00 00 00 00 - -# 80 - 87 (reserved) -00 00 00 00 00 00 00 00 - -# 88 - 95 (reserved) -00 00 00 00 00 00 00 00 - -# 96 - 103 (reserved) -00 00 00 00 00 00 00 00 - -# 104 - 111 (reserved) -00 00 00 00 00 00 00 00 - -# 112 - 116 (reserved) -00 00 00 00 00 - -# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code -# 0x0001 = AMD -00 01 - -# 119 Module ID: Module Manufacturing Location - oem specified -00 - -# 120 Module ID: Module Manufacture Year in BCD -# 0x13 = 2013 -# 121 Module ID: Module Manufacture week -# 0x12 = 12th week -13 12 - -# 122 - 125: Module Serial Number -00 00 00 00 - -# 126 - 127: Cyclical Redundancy Code -7b 97 -- To view, visit https://review.coreboot.org/c/coreboot/+/47723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65b3438def4b98609e6dabf588677a7214252b7b Gerrit-Change-Number: 47723 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003174 Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/kontron/mal10: Сlassify carrierboard by manufacturer
by Maxim Polyakov (Code Review) Aug. 7, 2023

Aug. 7, 2023

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47887 ) Change subject: mb/kontron/mal10: Сlassify carrierboard by manufacturer ...................................................................... mb/kontron/mal10: Сlassify carrierboard by manufacturer Add a subdirectory of carrier board manufacturers to classify according to manufacturer. Change-Id: I88a8b876eb5411dc6cb30901c9208737d07d6f29 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/kontron/mal10/Kconfig R src/mainboard/kontron/mal10/carriers/kontron/t10-tni/Makefile.inc R src/mainboard/kontron/mal10/carriers/kontron/t10-tni/board_info.txt R src/mainboard/kontron/mal10/carriers/kontron/t10-tni/gpio.c R src/mainboard/kontron/mal10/carriers/kontron/t10-tni/include/carrier/gpio.h R src/mainboard/kontron/mal10/carriers/kontron/t10-tni/overridetree.cb 6 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47887/1 diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig index 1705b91..1ce904f 100644 --- a/src/mainboard/kontron/mal10/Kconfig +++ b/src/mainboard/kontron/mal10/Kconfig @@ -41,7 +41,7 @@ config CARRIER_DIR string - default "t10-tni" if BOARD_KONTRON_T10_TNI + default "kontron/t10-tni" if BOARD_KONTRON_T10_TNI config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc b/src/mainboard/kontron/mal10/carriers/kontron/t10-tni/Makefile.inc similarity index 100% rename from src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc rename to src/mainboard/kontron/mal10/carriers/kontron/t10-tni/Makefile.inc diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt b/src/mainboard/kontron/mal10/carriers/kontron/t10-tni/board_info.txt similarity index 100% rename from src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt rename to src/mainboard/kontron/mal10/carriers/kontron/t10-tni/board_info.txt diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/kontron/t10-tni/gpio.c similarity index 100% rename from src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c rename to src/mainboard/kontron/mal10/carriers/kontron/t10-tni/gpio.c diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h b/src/mainboard/kontron/mal10/carriers/kontron/t10-tni/include/carrier/gpio.h similarity index 100% rename from src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h rename to src/mainboard/kontron/mal10/carriers/kontron/t10-tni/include/carrier/gpio.h diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/kontron/t10-tni/overridetree.cb similarity index 100% rename from src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb rename to src/mainboard/kontron/mal10/carriers/kontron/t10-tni/overridetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/47887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88a8b876eb5411dc6cb30901c9208737d07d6f29 Gerrit-Change-Number: 47887 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: screen fix
by Name of user not set (Code Review) Aug. 7, 2023

Aug. 7, 2023

Name of user not set #1002723 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39172 ) Change subject: screen fix ...................................................................... screen fix Change-Id: Ie68e77af77ccec83c29d3329ee9997b950b351f6 --- A grub.cfg A src/mainboard/dell/Kconfig A src/mainboard/dell/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Kconfig A src/mainboard/dell/dell_system_vostro_3360/Kconfig.name A src/mainboard/dell/dell_system_vostro_3360/Makefile.inc A src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl A src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl A src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c A src/mainboard/dell/dell_system_vostro_3360/board_info.txt A src/mainboard/dell/dell_system_vostro_3360/devicetree.cb A src/mainboard/dell/dell_system_vostro_3360/dsdt.asl A src/mainboard/dell/dell_system_vostro_3360/early_init.c A src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads A src/mainboard/dell/dell_system_vostro_3360/gpio.c A src/mainboard/dell/dell_system_vostro_3360/hda_verb.c A src/mainboard/dell/dell_system_vostro_3360/mainboard.c M util/superiotool/ite.c A util/superiotool/output 20 files changed, 1,275 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/39172/1 diff --git a/grub.cfg b/grub.cfg new file mode 100644 index 0000000..0e941ec --- /dev/null +++ b/grub.cfg @@ -0,0 +1 @@ +configfile (ahci0,3)/boot/grub/grub.cfg diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig new file mode 100755 index 0000000..298c62b --- /dev/null +++ b/src/mainboard/dell/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_DELL + +choice + prompt "Mainboard model" + +source "src/mainboard/dell/*/Kconfig.name" + +endchoice + +source "src/mainboard/dell/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "Dell Inc." + +endif # VENDOR_DELL diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name new file mode 100755 index 0000000..3d2fefd --- /dev/null +++ b/src/mainboard/dell/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_DELL + bool "Dell Inc." diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig b/src/mainboard/dell/dell_system_vostro_3360/Kconfig new file mode 100755 index 0000000..8861897 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig @@ -0,0 +1,43 @@ +if BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select GFX_GMA_INTERNAL_IS_LVDS + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default dell/dell_system_vostro_3360 + +config MAINBOARD_PART_NUMBER + string + default "Dell System Vostro 3360" + +config VGA_BIOS_FILE + string + default "pci8086,0156.rom" + +config VGA_BIOS_ID + string + default "8086,0156" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name new file mode 100755 index 0000000..8925217 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_DELL_SYSTEM_VOSTRO_3360 + bool "Dell System Vostro 3360" diff --git a/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc new file mode 100755 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/ec.asl diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl new file mode 100755 index 0000000..afb8abb --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi/superio.asl diff --git a/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c new file mode 100755 index 0000000..cfc2061 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/board_info.txt b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt new file mode 100755 index 0000000..be6bff8 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/board_info.txt @@ -0,0 +1,4 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb new file mode 100755 index 0000000..d234325 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/devicetree.cb @@ -0,0 +1,111 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "3000" + register "gpu_panel_power_backlight_on_delay" = "1700" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "300" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00040911" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1028 0x055c + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1028 0x055c + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1028 0x055c + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1028 0x055c + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1028 0x055c + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1028 0x055c + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1028 0x055c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1028 0x055c + end + device pci 1f.3 on # SMBus + subsystemid 0x1028 0x055c + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1028 0x055c + end + device pci 01.0 off # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1028 0x055c + end + end +end diff --git a/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl new file mode 100755 index 0000000..b00a7ff --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/dsdt.asl @@ -0,0 +1,29 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/early_init.c b/src/mainboard/dell/dell_system_vostro_3360/early_init.c new file mode 100755 index 0000000..6dbf226 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/early_init.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 0, 1, 3 }, + { 0, 1, 3 }, + { 1, 1, 4 }, + { 0, 1, 4 }, + { 1, 1, 5 }, + { 0, 1, 5 }, + { 1, 1, 6 }, + { 0, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads new file mode 100755 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/dell_system_vostro_3360/gpio.c b/src/mainboard/dell/dell_system_vostro_3360/gpio.c new file mode 100755 index 0000000..d7db210 --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/gpio.c @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c new file mode 100755 index 0000000..c55bf3c --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/hda_verb.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134213, /* Codec Vendor / Device ID: Cirrus */ + 0x1028055c, /* Subsystem ID */ + 6, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x1028055c), + AZALIA_PIN_CFG(0x0, 0x04, 0x0421101f), + AZALIA_PIN_CFG(0x0, 0x05, 0x90170010), + AZALIA_PIN_CFG(0x0, 0x06, 0x04a1103e), + AZALIA_PIN_CFG(0x0, 0x07, 0x40f000f0), + AZALIA_PIN_CFG(0x0, 0x08, 0x90a60030), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/dell_system_vostro_3360/mainboard.c b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c new file mode 100755 index 0000000..e5cfebf --- /dev/null +++ b/src/mainboard/dell/dell_system_vostro_3360/mainboard.c @@ -0,0 +1,15 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 81ab024..2f2cb57 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -274,6 +274,60 @@ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, {EOT}}}, + {0x8518, "IT8518", { + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x85,0x16, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x63,EOT}}, + {NOLDN, "Super I/O Control Register (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {NOLDN, "Super I/O Configuration Register (SIOIRQ)", + {0x25,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O General Purpose Register (SIOGP)", + {0x26,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O Power Mode Register (SIOPWR)", + {0x2d,EOT}, + {0x00,EOT}}, + {0x01, "UART1", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x03,0xf8,0x00,0x00,0x04,0x02,EOT}}, + {0x02, "UART2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x02,0xf8,0x00,0x00,0x04,0x02,EOT}}, + {0x04, "System Wakup-Up (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "Mouse", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0C,0x01,EOT}}, + {0x06, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71, + 0xf4,0xf5,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00, + NANA,NANA,EOT}}, + {0x10, "BRAM / Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71, + 0xf1,0xf2,0xf3,0xf4,0xf5,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x01, + NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x11, "Power Management Interface Channel 1", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Management Interface Channel 2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x01,0x01,EOT}}, + {0x17, "Power Management Interface Channel 3", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, + {EOT}}}, {0x8528, "IT8528", { {NOLDN, NULL, {0x24,0x25,0x26,0x27,0x28,0x29, @@ -1388,6 +1442,73 @@ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, + {0x8518, "IT8518", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, + 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, + 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, + 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, + 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, + 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, + 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7, + 0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {0x8987, "IT8987", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, diff --git a/util/superiotool/output b/util/superiotool/output new file mode 100644 index 0000000..fdf8a94 --- /dev/null +++ b/util/superiotool/output @@ -0,0 +1,500 @@ +superiotool r4.11-1185-g6824173704 +Found Aspeed AST2400 (id=0x00) at 0x4e +Register dump: +idx val def +0x20: 0x85 (0x00) +0x21: 0x18 (0x00) +0x22: 0x08 (0x00) +0x23: 0x01 (0x00) +0x24: 0x00 (0x00) +0x25: 0x00 (0x00) +0x26: 0x00 (0x00) +0x27: 0x00 (0x00) +0x28: 0x00 (0x00) +0x29: 0x00 (0x00) +0x2a: 0x00 (0x00) +0x2b: 0x00 (0x00) +0x2c: 0x01 (0x00) +0x2d: 0x00 (0x00) +0x2e: 0x00 (0x00) +0x2f: 0x00 (0x00) + +LDN 0x02 (SUART1) +idx val def +0x30: 0x00 (0x00) +0x60: 0x02 (0x03) +0x61: 0xf8 (0xf8) +0x70: 0x03 (0x04) +0x71: 0x02 (0x02) +0xf0: 0x00 (RR) + +LDN 0x03 (SUART2) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x02) +0x61: 0x00 (0xf8) +0x70: 0x00 (0x03) +0x71: 0x00 (0x02) +0xf0: 0x00 (0x00) + +LDN 0x04 (SWC) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x08) +0x61: 0x00 (0xe6) +0x62: 0x00 (0x08) +0x63: 0x00 (0xe0) +0x64: 0x00 (0x08) +0x65: 0x00 (0xe4) +0x66: 0x00 (0x08) +0x67: 0x00 (0xe8) +0x70: 0x00 (0x09) +0x71: 0x01 (0x01) + +LDN 0x05 (Keyboard config (KBC)) +idx val def +0x30: 0x01 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x60) +0x62: 0x00 (0x00) +0x63: 0x00 (0x64) +0x70: 0x0c (0x01) +0x71: 0x01 (0x02) +0x72: 0x00 (0x0c) +0x73: 0x00 (0x02) +0xf0: 0x00 (0x83) + +LDN 0x07 (GPIO) +idx val def +0x30: 0x00 (0x00) +0x38: 0x00 (0x00) +0x70: 0x00 (0x0b) +0x71: 0x00 (0x01) + +LDN 0x0b (SUART3) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x03) +0x61: 0x00 (0xe8) +0x70: 0x00 (0x06) +0x71: 0x00 (0x02) +0xf0: 0x00 (0x00) + +LDN 0x0c (SUART4) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x02) +0x61: 0x00 (0xe8) +0x70: 0x00 (0x05) +0x71: 0x00 (0x02) +0xf0: 0x00 (0x00) + +LDN 0x0d (iLPC2AHB) +idx val def +0x30: 0x00 (0x00) +0x70: 0x00 (0x09) +0x71: 0x00 (0x01) +0xf0: 0x00 (NA) +0xf1: 0x00 (NA) +0xf2: 0x00 (NA) +0xf3: 0x00 (NA) +0xf4: 0x00 (NA) +0xf5: 0x00 (NA) +0xf6: 0x00 (NA) +0xf7: 0x00 (NA) +0xf8: 0x00 (0x00) +0xfe: 0x00 (0x00) + +LDN 0x0e (Mailbox) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x08) +0x61: 0x00 (0xc0) +0x70: 0x00 (0x09) +0x71: 0x00 (0x01) + +Found ITE IT8516??? (id=0x8518, rev=0x8) at 0x4e +(Chip ID) +idx val def +0x20: 0x85 (0x85) +0x21: 0x18 (0x16) + +(Chip Version) +idx val def +0x22: 0x08 (0x63) + +(Super I/O Control Register (SIOCTRL)) +idx val def +0x23: 0x01 (0x01) + +(Super I/O Configuration Register (SIOIRQ)) +idx val def +0x25: 0x00 (0x00) + +(Super I/O General Purpose Register (SIOGP)) +idx val def +0x26: 0x00 (0x00) + +(Super I/O Power Mode Register (SIOPWR)) +idx val def +0x2d: 0x00 (0x00) + +LDN 0x01 (UART1) +idx val def +0x30: 0x00 (0x00) +0x60: 0x03 (0x03) +0x61: 0xf8 (0xf8) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x70: 0x04 (0x04) +0x71: 0x02 (0x02) + +LDN 0x02 (UART2) +idx val def +0x30: 0x00 (0x00) +0x60: 0x02 (0x02) +0x61: 0xf8 (0xf8) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x70: 0x03 (0x04) +0x71: 0x02 (0x02) + +LDN 0x04 (System Wakup-Up (SWUC)) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x70: 0x00 (0x00) +0x71: 0x01 (0x01) + +LDN 0x05 (Mouse) +idx val def +0x30: 0x01 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x70: 0x0c (0x0c) +0x71: 0x01 (0x01) + +LDN 0x06 (Keyboard) +idx val def +0x30: 0x01 (0x00) +0x60: 0x00 (0x00) +0x61: 0x60 (0x60) +0x62: 0x00 (0x00) +0x63: 0x64 (0x64) +0x70: 0x01 (0x01) +0x71: 0x01 (0x01) + +LDN 0x0f (Shared Memory/Flash Interface (SMFI)) +idx val def +0x30: 0x00 (0x00) +0x60: 0x00 (0x00) +0x61: 0x00 (0x00) +0x62: 0x00 (0x00) +0x63: 0x00 (0x00) +0x70: 0x00 (0x00) +0x71: 0x00 (0x00) +0xf4: 0x00 (NA) +0xf5: 0x00 (NA) + +LDN 0x10 (BRAM / Real Time Clock (RTC)) +idx val def +0x30: 0x01 (0x00) +0x60: 0x00 (0x00) +0x61: 0x70 (0x70) +0x62: 0x09 (0x00) +0x63: 0x10 (0x72) +0x70: 0x08 (0x08) +0x71: 0x01 (0x01) +0xf1: 0x00 (NA) +0xf2: 0x00 (NA) +0xf3: 0x00 (NA) +0xf4: 0x3f (NA) +0xf5: 0x3f (NA) + +LDN 0x11 (Power Management Interface Channel 1) +idx val def +0x30: 0x01 (0x00) +0x60: 0x00 (0x00) +0x61: 0x62 (0x62) +0x62: 0x00 (0x00) +0x63: 0x66 (0x66) +0x70: 0x00 (0x01) +0x71: 0x01 (0x01) + +LDN 0x12 (Power Management Interface Channel 2) +idx val def +0x30: 0x01 (0x00) +0x60: 0x00 (0x00) +0x61: 0x68 (0x68) +0x62: 0x00 (0x00) +0x63: 0x6c (0x6c) +0x70: 0x00 (0x01) +0x71: 0x01 (0x01) + +LDN 0x17 (Power Management Interface Channel 3) +idx val def +0x30: 0x01 (0x00) +0x60: 0x06 (0x00) +0x61: 0xa0 (0x6a) +0x62: 0x06 (0x00) +0x63: 0xa4 (0x6e) +0x70: 0x01 (0x01) +0x71: 0x01 (0x01) + +Environment controller (0x0005) +BRAM (0x0910) +Register dump: +idx val def +0x00: 0x12 (NA) +0x01: 0x03 (NA) +0x02: 0x00 (NA) +0x03: 0x00 (NA) +0x04: 0x01 (NA) +0x05: 0x00 (NA) +0x06: 0x02 (NA) +0x07: 0x00 (NA) +0x08: 0xa3 (NA) +0x09: 0xff (NA) +0x0a: 0xff (NA) +0x0b: 0x00 (NA) +0x0c: 0x00 (NA) +0x0d: 0x00 (NA) +0x0e: 0x00 (NA) +0x0f: 0x00 (NA) + +Register dump: +idx val def +0x10: 0x00 (NA) +0x11: 0x00 (NA) +0x12: 0x00 (NA) +0x13: 0x00 (NA) +0x14: 0x00 (NA) +0x15: 0x00 (NA) +0x16: 0x00 (NA) +0x17: 0x00 (NA) +0x18: 0x00 (NA) +0x19: 0x00 (NA) +0x1a: 0x00 (NA) +0x1b: 0x00 (NA) +0x1c: 0x00 (NA) +0x1d: 0x00 (NA) +0x1e: 0x02 (NA) +0x1f: 0x00 (NA) + +Register dump: +idx val def +0x20: 0x01 (NA) +0x21: 0x10 (NA) +0x22: 0x00 (NA) +0x23: 0x00 (NA) +0x24: 0x00 (NA) +0x25: 0x00 (NA) +0x26: 0x00 (NA) +0x27: 0x00 (NA) +0x28: 0x00 (NA) +0x29: 0x00 (NA) +0x2a: 0x00 (NA) +0x2b: 0x00 (NA) +0x2c: 0x00 (NA) +0x2d: 0x00 (NA) +0x2e: 0x00 (NA) +0x2f: 0x00 (NA) + +Register dump: +idx val def +0x30: 0x00 (NA) +0x31: 0x00 (NA) +0x32: 0x24 (NA) +0x33: 0x00 (NA) +0x34: 0x00 (NA) +0x35: 0x10 (NA) +0x36: 0x00 (NA) +0x37: 0x00 (NA) +0x38: 0x00 (NA) +0x39: 0x00 (NA) +0x3a: 0x88 (NA) +0x3b: 0x27 (NA) +0x3c: 0x68 (NA) +0x3d: 0x00 (NA) +0x3e: 0x00 (NA) +0x3f: 0x00 (NA) + +Register dump: +idx val def +0x40: 0x00 (NA) +0x41: 0x00 (NA) +0x42: 0x00 (NA) +0x43: 0x00 (NA) +0x44: 0x00 (NA) +0x45: 0x00 (NA) +0x46: 0x00 (NA) +0x47: 0x00 (NA) +0x48: 0x00 (NA) +0x49: 0x00 (NA) +0x4a: 0x00 (NA) +0x4b: 0x00 (NA) +0x4c: 0x00 (NA) +0x4d: 0x00 (NA) +0x4e: 0x00 (NA) +0x4f: 0x00 (NA) + +Register dump: +idx val def +0x50: 0x00 (NA) +0x51: 0x00 (NA) +0x52: 0x00 (NA) +0x53: 0x00 (NA) +0x54: 0x00 (NA) +0x55: 0x00 (NA) +0x56: 0x00 (NA) +0x57: 0x00 (NA) +0x58: 0x00 (NA) +0x59: 0x00 (NA) +0x5a: 0x00 (NA) +0x5b: 0x00 (NA) +0x5c: 0x00 (NA) +0x5d: 0x00 (NA) +0x5e: 0x00 (NA) +0x5f: 0x00 (NA) + +Register dump: +idx val def +0x60: 0x00 (NA) +0x61: 0x00 (NA) +0x62: 0x00 (NA) +0x63: 0x00 (NA) +0x64: 0x00 (NA) +0x65: 0x00 (NA) +0x66: 0x00 (NA) +0x67: 0x00 (NA) +0x68: 0x00 (NA) +0x69: 0x00 (NA) +0x6a: 0x00 (NA) +0x6b: 0x00 (NA) +0x6c: 0x00 (NA) +0x6d: 0x00 (NA) +0x6e: 0x00 (NA) +0x6f: 0x00 (NA) + +Register dump: +idx val def +0x70: 0x00 (NA) +0x71: 0x00 (NA) +0x72: 0x00 (NA) +0x73: 0x00 (NA) +0x74: 0x00 (NA) +0x75: 0x00 (NA) +0x76: 0x00 (NA) +0x77: 0x00 (NA) +0x78: 0x00 (NA) +0x79: 0x00 (NA) +0x7a: 0x00 (NA) +0x7b: 0x00 (NA) +0x7c: 0x00 (NA) +0x7d: 0x00 (NA) +0x7e: 0x00 (NA) +0x7f: 0x00 (NA) + +Register dump: +idx val def +0x80: 0x12 (NA) +0x81: 0x03 (NA) +0x82: 0x00 (NA) +0x83: 0x00 (NA) +0x84: 0x01 (NA) +0x85: 0x00 (NA) +0x86: 0x02 (NA) +0x87: 0x00 (NA) +0x88: 0xa3 (NA) +0x89: 0xff (NA) +0x8a: 0xff (NA) +0x8b: 0x00 (NA) +0x8c: 0x00 (NA) +0x8d: 0x00 (NA) +0x8e: 0x00 (NA) +0x8f: 0x00 (NA) + +Register dump: +idx val def +0x90: 0x00 (NA) +0x91: 0x00 (NA) +0x92: 0x00 (NA) +0x93: 0x00 (NA) +0x94: 0x00 (NA) +0x95: 0x00 (NA) +0x96: 0x00 (NA) +0x97: 0x00 (NA) +0x98: 0x00 (NA) +0x99: 0x00 (NA) +0x9a: 0x00 (NA) +0x9b: 0x00 (NA) +0x9c: 0x00 (NA) +0x9d: 0x00 (NA) +0x9e: 0x02 (NA) +0x9f: 0x00 (NA) + +Register dump: +idx val def +0xa0: 0x01 (NA) +0xa1: 0x10 (NA) +0xa2: 0x00 (NA) +0xa3: 0x00 (NA) +0xa4: 0x00 (NA) +0xa5: 0x00 (NA) +0xa6: 0x00 (NA) +0xa7: 0x00 (NA) +0xa8: 0x00 (NA) +0xa9: 0x00 (NA) +0xaa: 0x00 (NA) +0xab: 0x00 (NA) +0xac: 0x00 (NA) +0xad: 0x00 (NA) +0xae: 0x00 (NA) +0xaf: 0x00 (NA) + +Register dump: +idx val def +0xb0: 0x00 (NA) +0xb1: 0x00 (NA) +0xb2: 0x24 (NA) +0xb3: 0x00 (NA) +0xb4: 0x00 (NA) +0xb5: 0x10 (NA) +0xb6: 0x00 (NA) +0xb7: 0x00 (NA) +0xb8: 0x00 (NA) +0xb9: 0x00 (NA) +0xba: 0x88 (NA) +0xbb: 0x27 (NA) +0xbc: 0x68 (NA) +0xbd: 0x00 (NA) +0xbe: 0x00 (NA) +0xbf: 0x00 (NA) + +Register dump: +idx val def +0xc0: 0x00 (NA) +0xc1: 0x00 (NA) +0xc2: 0x00 (NA) +0xc3: 0x00 (NA) +0xc4: 0x00 (NA) +0xc5: 0x00 (NA) +0xc6: 0x00 (NA) +0xc7: 0x00 (NA) +0xc8: 0x00 (NA) +0xc9: 0x00 (NA) +0xca: 0x00 (NA) +0xcb: 0x00 (NA) +0xcc: 0x00 (NA) +0xcd: 0x00 (NA) +0xce: 0x00 (NA) +0xcf: 0x00 (NA) + +Found SMSC SCH5317 (id=0x85, rev=0x18) at 0x4e +No dump available for this Super I/O +No extra registers known for this chip. -- To view, visit https://review.coreboot.org/c/coreboot/+/39172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie68e77af77ccec83c29d3329ee9997b950b351f6 Gerrit-Change-Number: 39172 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002723 Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: src/mainboard/{intel/google}: Include ASL for additional PCI segment
by Subrata Banik (Code Review) Aug. 7, 2023

Aug. 7, 2023

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41012 ) Change subject: src/mainboard/{intel/google}: Include ASL for additional PCI segment ...................................................................... src/mainboard/{intel/google}: Include ASL for additional PCI segment This patch allows mainboard to include static ASL for TBT PCI segment extracted build/dsdt.aml Device (PCI1) { Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, One) // _SEG: PCI Segment Name (_UID, One) // _UID: Unique ID Name (_ADR, Zero) // _ADR: Address .... } Change-Id: I3601aa4e9002334fd80fc86ced9e1df2afc739b5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl 3 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41012/1 diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 631ec5e..6359feb 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -30,6 +30,9 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> } +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + #include <soc/intel/common/block/acpi/acpi/pcisegment.asl> +#endif } /* Chrome OS specific */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index a87c743..9a83359 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -33,6 +33,9 @@ #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + #include <soc/intel/common/block/acpi/acpi/pcisegment.asl> +#endif /* Mainboard hooks */ #include "mainboard.asl" } diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index c66e972..60275cc 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -29,6 +29,9 @@ #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + #include <soc/intel/common/block/acpi/acpi/pcisegment.asl> +#endif } #if CONFIG(CHROMEOS) -- To view, visit https://review.coreboot.org/c/coreboot/+/41012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3601aa4e9002334fd80fc86ced9e1df2afc739b5 Gerrit-Change-Number: 41012 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: sb/amd/agesa/hudson: Use common FCH HDA setup code
by Paul Menzel (Code Review) Aug. 7, 2023

Aug. 7, 2023

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46639 ) Change subject: sb/amd/agesa/hudson: Use common FCH HDA setup code ...................................................................... sb/amd/agesa/hudson: Use common FCH HDA setup code Let’s configure Azalia ourselves instead of AGESA, and use the common AMD code, where `hda.c` is basically the same. The FCH hasn’t changed in this regard, so the code can be easily used. Note, the board change, will be split out. For whatever reason, the ACPI device AZHD is not created (at least I do not see it in the disassembled SSDT). Change-Id: I368947e578a8c4c97af190103ffb42adb1f8d4e6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/Kconfig A src/mainboard/asus/f2a85-m/hda_verb.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc D src/southbridge/amd/agesa/hudson/hda.c 5 files changed, 35 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46639/1 diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index 27d5517..7d475c2 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -17,6 +17,7 @@ select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO select BOARD_ROMSIZE_KB_8192 select GFXUMA + select AZALIA_PLUGIN_SUPPORT choice prompt "DDR3 memory voltage" diff --git a/src/mainboard/asus/f2a85-m/hda_verb.c b/src/mainboard/asus/f2a85-m/hda_verb.c new file mode 100644 index 0000000..0fec04e --- /dev/null +++ b/src/mainboard/asus/f2a85-m/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC701 on mainboard */ + 0x10ec0892, + + AZALIA_SUBVENDOR(0, 0x10438444), // HDA Codec Subsystem ID: Subsystem: + // ASUSTeK Computer Inc. FCH Azalia Controller + + AZALIA_RESET(1), // Widget node 0x01 : + AZALIA_PIN_CFG(0, 0x11, 0x99430140), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19850), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x01456130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0xff, 0xffffffff) +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index e61bc85..24ddc26 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -17,6 +17,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_HDA config EHCI_BAR hex diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b8eb5b9..de9afba 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -9,7 +9,6 @@ ramstage-y += sm.c ramstage-y += ide.c ramstage-y += sata.c -ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c deleted file mode 100644 index a15b045..0000000 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#include "hudson.h" - -static void hda_init(struct device *dev) -{ -} - -static struct device_operations hda_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = hda_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_HDA, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368947e578a8c4c97af190103ffb42adb1f8d4e6 Gerrit-Change-Number: 46639 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Add support for calling microcode update API
by Sugnan Prabhu S (Code Review) Aug. 7, 2023

Aug. 7, 2023

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46844 ) Change subject: soc/intel/jasperlake: Add support for calling microcode update API ...................................................................... soc/intel/jasperlake: Add support for calling microcode update API This adds the entry function to call the main microcode update interface to enable microcode update for Jasperlake SoC and also implements the reboot function required. BUG=b:149547271 TEST=Build and boot JSLRVP to OS Change-Id: I49dec0f764f74fbd8caa0e15a932dcc4d4b90aaa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/ucode_update.c 2 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46844/1 diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..d32bf86 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += systemagent.c ramstage-y += sd.c ramstage-y += me.c +ramstage-$(CONFIG_INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE) += ucode_update.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/jasperlake/ucode_update.c b/src/soc/intel/jasperlake/ucode_update.c new file mode 100644 index 0000000..cfe894b --- /dev/null +++ b/src/soc/intel/jasperlake/ucode_update.c @@ -0,0 +1,50 @@ + +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootstate.h> +#include <console/console.h> +#include <halt.h> +#include <intelbasecode/ucode_update.h> +#include <reset.h> +#include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> +#include <soc/intel/common/reset.h> +#include <vb2_api.h> + +static void update_ucode(void *unused) +{ + struct vb2_context *ctx; + + if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) { + if (update_ucode_and_topswap_state()) { + /* Update failed */ + if (CONFIG(VBOOT)) { + printk(BIOS_DEBUG, "ucode: Failed to update microcode\n"); + ctx = vboot_get_context(); + if (ctx == NULL) + die("ucode: Failed to trigger recovery mode\n"); + vb2api_fail(ctx, 0x36, 0x0); + vboot_save_data(ctx); + vboot_reboot(); + } + } + } +} + +void ucode_update_reboot(void) +{ + if (CONFIG(VBOOT)) + vboot_reboot(); + else + do_board_reset(); + + die("ucode: Failed to reset the system\n"); + halt(); +} + +int ucode_update_rec_mode_enabled(void) +{ + return vboot_recovery_mode_enabled(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, update_ucode, NULL); + -- To view, visit https://review.coreboot.org/c/coreboot/+/46844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49dec0f764f74fbd8caa0e15a932dcc4d4b90aaa Gerrit-Change-Number: 46844 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Add code to configure who decodes IO 0x80
by Arthur Heymans (Code Review) Aug. 7, 2023

Aug. 7, 2023

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47164 ) Change subject: sb/intel/common: Add code to configure who decodes IO 0x80 ...................................................................... sb/intel/common: Add code to configure who decodes IO 0x80 Change-Id: Ieb973c369c0061867320c255df5ae85fb5101276 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/post.c A src/southbridge/intel/common/post.h 4 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47164/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 3030d25..74f0252 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -105,3 +105,6 @@ hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS default 0x400 + +config SOUTHBRIDGE_INTEL_COMMON_POST + def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1ededd2..50dda9b 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -3,6 +3,8 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_POST) += post.c + all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c diff --git a/src/southbridge/intel/common/post.c b/src/southbridge/intel/common/post.c new file mode 100644 index 0000000..96155d1 --- /dev/null +++ b/src/southbridge/intel/common/post.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> + +#include "rcba.h" + +#define GCS 0x3410 +#define RPR (1 << 2) + +void configure_port80(void) +{ + if (CONFIG(POST_DEVICE_LPC)) + RCBA32_AND_OR(GCS, ~RPR, 0); + else if (CONFIG(POST_DEVICE_PCI_PCIE)) + RCBA32_AND_OR(GCS, RPR, RPR); +} diff --git a/src/southbridge/intel/common/post.h b/src/southbridge/intel/common/post.h new file mode 100644 index 0000000..f64fce5 --- /dev/null +++ b/src/southbridge/intel/common/post.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_POST_H +#define SOUTHBRIDGE_INTEL_COMMON_POST_H + +/* Configure where IO port 0x80 writes (POST) get forwarded (PCI/LPC). + * Note that port 0x90 writes which aliases port 0x80 always get forwarded + * to LPC. + */ +void configure_port80(void); + +#endif + -- To view, visit https://review.coreboot.org/c/coreboot/+/47164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb973c369c0061867320c255df5ae85fb5101276 Gerrit-Change-Number: 47164 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2
by Patrick Rudolph (Code Review) Aug. 7, 2023

Aug. 7, 2023

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33107 Change subject: [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2 ...................................................................... [RFC]lib/coreboot_tables: Introduce BOOT_MEDIA_PARAMS2 BOOT_MEDIA_PARAMS2 exposes the boot media MMIO address if it's memory mapped in addition to various regions inside the bootmedia. That information can be used by payloads to: * Support VBOOT on SeaBIOS, as it otherwise uses the RO CBFS only * Support Intel Apollolake and platforms that don't map the end of the BIOS region to the end of the address space * Support fwupd and flashrom finding the FMAP in memory Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c 2 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/33107/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 198ad27..a854e44 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -392,6 +392,81 @@ struct mac_address mac_addrs[0]; }; +/** + * coreboot boot media params2 + * + * The coreboot 'boot media params2' contain information about the + * bootmedia layout, allowing a payload to read the boot media + * without the need to parse (platform specific) layout files. + * + * It extends 'boot media params' by MMIO addresses and a second CBFS + * pointer. + * + * If the boot media is memory mapped, as it's usually done on x86 platforms, + * the FMAP and CBFS can be easily accessed by any software without the need + * for platform specific drivers. + * + * If the boot media is not memory mapped, the `mmap_mmio_address` is set + * to ~0ULL. In that case the software must use platform specific drivers + * to access the boot media (like flashrom or Linux's MTD). + * + * The memory mapped area is `mmap_size` bytes in size, starting `mmap_offset` + * bytes from `mmap_mmio_address`. + * The memory mapped area might be smaller than `boot_media_size` bytes, + * which gives the total size in bytes as seen by an external programmer. + * + * Software utilizing the coreboot boot media params2 shall check if the + * region to be access falls completely within the memory mapped region, + * before trying to access them. + * In addition it should not assume that the whole boot media is memory mapped. + * + * Example on Intel Apollolake: + * + * physical memory boot media + * +-----------+ + * | | + * | | + * +-----------+ MMAP MMIO address +-----------------+ -------- + * | ~UNAVAIL~ | | | IFD | | | | | + * | | MMAP offset | | | | | | + * | | | | | | | | | + * +-----------+ --- <<< +-----------------+ | | | | + * | BIOS REG | | | BIOS | | | | | + * | | | | | | | | | + * | | | |+---------------+| --+-+-+-+CBFS offset + * | | | || CBFS Active || | | | + * | | MMAP size |+---------------+| --+-+-+FMAP offset + * | | | || FMAP || | | + * | | | |+---------------+| --+-+CBFS legacy offset + * | | | || COREBOOT(CBFS)|| | + * +-----------+ --- <<< |+---------------+| | + * | TXE SRAM | || BIOS UNUSABLE || | + * | | |+---------------+| | + * +-----------+ +-----------------+ | + * |DEVICE EXTENSION | | + * | | | + * +-----------------+ -+Boot media size + */ + +#define LB_TAG_BOOT_MEDIA_PARAMS2 0x0036 +struct lb_boot_media_params2 { + uint32_t tag; + uint32_t size; + /* offsets are relative to start of boot media */ + uint64_t fmap_offset; + uint64_t cbfs_offset; + uint64_t cbfs_legacy_offset; + uint64_t mmap_offset; + /* Size is in bytes */ + uint64_t cbfs_size; + uint64_t fmap_size; + uint64_t boot_media_size; + uint64_t cbfs_legacy_size; + uint64_t mmap_size; + /* MMIO address of MMAPed boot media, ~0ULL if not MMAPed.*/ + uint64_t mmap_mmio_address; +}; + #define LB_TAG_SERIALNO 0x002a #define MAX_SERIALNO_LENGTH 32 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d..c5807fd 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -261,8 +261,10 @@ static void lb_boot_media_params(struct lb_header *header) { struct lb_boot_media_params *bmp; + struct lb_boot_media_params2 *bmp2; struct cbfs_props props; const struct region_device *boot_dev; + struct region ar; struct region_device fmrd; boot_device_init(); @@ -285,6 +287,47 @@ bmp->fmap_offset = ~(uint64_t)0; if (find_fmap_directory(&fmrd) == 0) bmp->fmap_offset = region_device_offset(&fmrd); + + /* LB_TAG_BOOT_MEDIA_PARAMS2 exposes additional parameters: + * - MMAPed boot media address + * - legacy CBFS position (RO partition in case of VBOOT) + */ + bmp2 = (struct lb_boot_media_params2 *)lb_new_record(header); + bmp2->tag = LB_TAG_BOOT_MEDIA_PARAMS2; + bmp2->size = sizeof(*bmp2); + + bmp2->cbfs_offset = bmp->cbfs_offset; + bmp2->cbfs_size = bmp->cbfs_size; + bmp2->boot_media_size = bmp->boot_media_size; + bmp2->fmap_offset = bmp->fmap_offset; + + if (find_fmap_directory(&fmrd) == 0) + bmp2->fmap_size = region_device_size(&fmrd); + + if (fmap_locate_area("COREBOOT", &ar)) { + printk(BIOS_INFO, "Can't find 'COREBOOT' area in FMAP\n"); + bmp2->cbfs_legacy_offset = ~(uint64_t)0; + bmp2->cbfs_legacy_size = 0; + } else { + bmp2->cbfs_legacy_offset = ar.offset; + bmp2->cbfs_legacy_size = ar.size; + } + + if (CONFIG(COMMON_CBFS_SPI_WRAPPER)) { + /* rdev_mmap will return a pointer to _postram_cbfs_cache */ + bmp2->mmap_offset = ~(uint64_t)0; + bmp2->mmap_size = 0; + bmp2->mmap_mmio_address = ~(uint64_t)0; + } else { + /* FIXME: Introduce API to set correct values here */ + bmp2->mmap_offset = 0; + bmp2->mmap_size = bmp2->boot_media_size; + /* Get address to MMAP boot media */ + uintptr_t off = (uintptr_t)rdev_mmap(boot_dev, 0, + bmp2->mmap_size); + bmp2->mmap_mmio_address = off; + rdev_munmap(boot_dev, (void *)off); + } } static void lb_ram_code(struct lb_header *header) -- To view, visit https://review.coreboot.org/c/coreboot/+/33107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b1ac927b8782cc99cd7f34d8bf5c4ef60b5570 Gerrit-Change-Number: 33107 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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