coreboot-gerrit July 2022

coreboot-gerrit@coreboot.org

673 discussions

Change in coreboot[master]: WIP:src/amd/common: Detect SOC type before access SPI 0x2C
by Bao Zheng (Code Review) 07 Aug '23

07 Aug '23

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48955 to review the following change. Change subject: WIP:src/amd/common: Detect SOC type before access SPI 0x2C ...................................................................... WIP:src/amd/common: Detect SOC type before access SPI 0x2C Change-Id: Id493597b3854296a285d2337b7cf9fd01394d169 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/spi/fch_spi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/48955/1 diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index c39147a..910521a 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -60,6 +60,7 @@ { lpc_enable_spi_rom(SPI_ROM_ENABLE); lpc_enable_spi_prefetch(); - fch_spi_disable_4dw_burst(); + if (!CONFIG(SOC_AMD_CEZANNE)) + fch_spi_disable_4dw_burst(); fch_spi_config_modes(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id493597b3854296a285d2337b7cf9fd01394d169 Gerrit-Change-Number: 48955 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: [UNTESTED] sb/intel/bd82x6x: Handle root port lane mapping
by Angel Pons (Code Review) 07 Aug '23

07 Aug '23

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49171 ) Change subject: [UNTESTED] sb/intel/bd82x6x: Handle root port lane mapping ...................................................................... [UNTESTED] sb/intel/bd82x6x: Handle root port lane mapping PCH PCIe lane-to-port mapping can be configured through IFD straps. Depending on the strapped port widths, some registers need to be programmed differently. The same logic applies to the two groups of four lanes/ports, but the register offsets are different. Change-Id: Icb8b8280ab51c736417f202fc30d6ab486b388a8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 35 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/49171/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index f684a96..903dc01 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -135,6 +135,40 @@ ; } +static void pch_assign_pcie_lane_mapping(void) +{ + const u32 rpc = RCBA32(RPC); + + for (unsigned int group = 0; group < 2; group++) { + + const u32 group_base = 0xec000403 + 0x400 * group; + + const unsigned int group_offset = 22 - 2 * group; + + switch (rpc >> (2 * group) & 3) { + case 3: /* x4 */ + RCBA32_AND_OR(0x2310, ~(3 << group_offset), 2 << group_offset); + + pch_iobp_update(group_base + 0x100, ~(0x1f << 27), (1 << 2 | 1) << 27); + pch_iobp_update(group_base + 0x200, ~(0x1f << 27), (2 << 2 | 1) << 27); + pch_iobp_update(group_base + 0x300, ~(0x1f << 27), (3 << 2 | 1) << 27); + break; + + case 2: /* x2, x2 */ + RCBA32_AND_OR(0x2310, ~(3 << group_offset), 1 << group_offset); + + pch_iobp_update(group_base + 0x100, ~(0x1f << 27), (1 << 2 | 1) << 27); + pch_iobp_update(group_base + 0x300, ~(0x1f << 27), (1 << 2 | 1) << 27); + break; + + case 1: /* x2, x1, x1 */ + case 0: /* x1, x1, x1, x1 */ + default: + RCBA32_AND_OR(0x2310, ~(3 << group_offset), 0); + } + } +} + void early_pch_init_native(void) { /* Lock down PMBASE */ @@ -148,10 +182,7 @@ RCBA32_AND_OR(0x2310, ~(3 << 29), 1 << 29); RCBA32(DMC2) = 0x00854c74; - /* TODO: Handle non-zero cases */ - RCBA8(RPC); - RCBA32_AND_OR(0x2310, ~(3 << 22), 0); - RCBA32_AND_OR(0x2310, ~(3 << 20), 0); + pch_assign_pcie_lane_mapping(); write_iobp(0xea007f62, 0x00590133); write_iobp(0xec007f62, 0x00590133); -- To view, visit https://review.coreboot.org/c/coreboot/+/49171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb8b8280ab51c736417f202fc30d6ab486b388a8 Gerrit-Change-Number: 49171 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: device/Kconfig: Use more fine grained Kconfig for graphics init
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49174 ) Change subject: device/Kconfig: Use more fine grained Kconfig for graphics init ...................................................................... device/Kconfig: Use more fine grained Kconfig for graphics init Add MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT. Change-Id: I3e175f0377c3c03ae93148e1178136cc0ccaad52 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/Kconfig M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/foxconn/d41s/Kconfig M src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig M src/mainboard/intel/d510mo/Kconfig M src/mainboard/intel/d945gclf/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig 8 files changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49174/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a472a6a..789e239 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -39,6 +39,13 @@ Selected by mainboards / drivers that provide native graphics init within coreboot. +config MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT + def_bool n + select MAINBOARD_HAS_NATIVE_VGA_INIT + help + Selected by mainboards / drivers that provide native graphics + init for Intel GPUs within coreboot. + config MAINBOARD_FORCE_NATIVE_VGA_INIT def_bool n depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index a0dc96e7..280cf8c 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -15,7 +15,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select INTEL_GMA_HAVE_VBT select NO_CBFS_MCACHE diff --git a/src/mainboard/foxconn/d41s/Kconfig b/src/mainboard/foxconn/d41s/Kconfig index 93ce389..47b0b4c 100644 --- a/src/mainboard/foxconn/d41s/Kconfig +++ b/src/mainboard/foxconn/d41s/Kconfig @@ -11,7 +11,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig index f6a99e7..e013ed2 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig @@ -15,7 +15,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L select INTEL_GMA_HAVE_VBT select NO_CBFS_MCACHE diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index cd6260b..0482dab 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -11,7 +11,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select INTEL_INT15 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 06e1a0c..e2ab01e 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -16,7 +16,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d6498f1..091d2f1 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -31,7 +31,7 @@ config I945_LVDS def_bool n - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT help Selected by mainboards that use native graphics initialization diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 185beebe..962825a 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -9,7 +9,7 @@ def_bool y select HAVE_DEBUG_RAM_SETUP select VGA - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_INTEL_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/49174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e175f0377c3c03ae93148e1178136cc0ccaad52 Gerrit-Change-Number: 49174 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: device/Kconfig: Use more fine grained Kconfig for graphics init
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49175 ) Change subject: device/Kconfig: Use more fine grained Kconfig for graphics init ...................................................................... device/Kconfig: Use more fine grained Kconfig for graphics init Add MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT. Change-Id: Iee2d7d89a54418a5a93a57da37462c5cfb17c11c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/Kconfig M src/drivers/aspeed/ast2050/Kconfig 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/49175/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 789e239..baa7110 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -46,6 +46,13 @@ Selected by mainboards / drivers that provide native graphics init for Intel GPUs within coreboot. +config MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT + def_bool n + select MAINBOARD_HAS_NATIVE_VGA_INIT + help + Selected by mainboards / drivers that provide native graphics + init for Aspeed GPUs within coreboot. + config MAINBOARD_FORCE_NATIVE_VGA_INIT def_bool n depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT diff --git a/src/drivers/aspeed/ast2050/Kconfig b/src/drivers/aspeed/ast2050/Kconfig index 7d2c728..5023b1f 100644 --- a/src/drivers/aspeed/ast2050/Kconfig +++ b/src/drivers/aspeed/ast2050/Kconfig @@ -1,4 +1,4 @@ config DRIVERS_ASPEED_AST2050 bool select DRIVERS_ASPEED_AST_COMMON - select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT -- To view, visit https://review.coreboot.org/c/coreboot/+/49175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2d7d89a54418a5a93a57da37462c5cfb17c11c Gerrit-Change-Number: 49175 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: arch/riscv: Use same indents for switch/case
by Felix Singer (Code Review) 07 Aug '23

07 Aug '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49203 ) Change subject: arch/riscv: Use same indents for switch/case ...................................................................... arch/riscv: Use same indents for switch/case Use same indents for switch/case to fix linter issues. Change-Id: I004103113e4002dded95f804d44bab7c7c4e7c43 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/arch/riscv/trap_handler.c 1 file changed, 29 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/49203/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 32b2c40..6147a20 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -32,10 +32,10 @@ static const char *mstatus_to_previous_mode(uintptr_t ms) { switch (ms & MSTATUS_MPP) { - case 0x00000000: return "user"; - case 0x00000800: return "supervisor"; - case 0x00001000: return "hypervisor"; - case 0x00001800: return "machine"; + case 0x00000000: return "user"; + case 0x00000800: return "supervisor"; + case 0x00001000: return "hypervisor"; + case 0x00001800: return "machine"; } return "unknown"; @@ -116,31 +116,31 @@ } switch (tf->cause) { - case CAUSE_MISALIGNED_FETCH: - case CAUSE_FETCH_ACCESS: - case CAUSE_ILLEGAL_INSTRUCTION: - case CAUSE_BREAKPOINT: - case CAUSE_LOAD_ACCESS: - case CAUSE_STORE_ACCESS: - case CAUSE_USER_ECALL: - case CAUSE_HYPERVISOR_ECALL: - case CAUSE_MACHINE_ECALL: - print_trap_information(tf); - break; - case CAUSE_SUPERVISOR_ECALL: - handle_sbi(tf); - return; - case CAUSE_MISALIGNED_LOAD: - case CAUSE_MISALIGNED_STORE: - print_trap_information(tf); - handle_misaligned(tf); - return; - default: - printk(BIOS_EMERG, "================================\n"); - printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); - printk(BIOS_EMERG, "================================\n"); - print_trap_information(tf); - break; + case CAUSE_MISALIGNED_FETCH: + case CAUSE_FETCH_ACCESS: + case CAUSE_ILLEGAL_INSTRUCTION: + case CAUSE_BREAKPOINT: + case CAUSE_LOAD_ACCESS: + case CAUSE_STORE_ACCESS: + case CAUSE_USER_ECALL: + case CAUSE_HYPERVISOR_ECALL: + case CAUSE_MACHINE_ECALL: + print_trap_information(tf); + break; + case CAUSE_SUPERVISOR_ECALL: + handle_sbi(tf); + return; + case CAUSE_MISALIGNED_LOAD: + case CAUSE_MISALIGNED_STORE: + print_trap_information(tf); + handle_misaligned(tf); + return; + default: + printk(BIOS_EMERG, "================================\n"); + printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); + printk(BIOS_EMERG, "================================\n"); + print_trap_information(tf); + break; } die("Can't recover from trap. Halting.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/49203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I004103113e4002dded95f804d44bab7c7c4e7c43 Gerrit-Change-Number: 49203 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/tigerlake: Add Method _L73 for USB overcurrent indication
by John Zhao (Code Review) 07 Aug '23

07 Aug '23

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47656 ) Change subject: soc/intel/tigerlake: Add Method _L73 for USB overcurrent indication ...................................................................... soc/intel/tigerlake: Add Method _L73 for USB overcurrent indication There is a ACPI error message about no handler or method for GPE73 while plugging a USB3 flash driver to a type-C-to-A dongle. The PMC_GPE0_DW2 is routed to GPP_E and GPP_E9/USB_OC0# is mapped to GPE73. This change adds a dummy GPE Method _L73 for USB overcurrent indication. Kernel driver suspends the bus and host controller which avoids the host halted in USB overcurrent state. BUG=b:155158498;173054070 TEST=Built images for Voxel and Delbin boards. Verified GPE73 is enabled and unmasked. There is no handler or method error message for GPE73 while plugging a USB3 flash driver to a type-C-to-A dongle. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I25fca6de44ce5c513fb6f7c4cfe46c5b7686fb20 --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47656/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9893833..d888e86 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -311,6 +311,12 @@ \_SB.PCI0.TRP2.HPME() \_SB.PCI0.TRP3.HPME() } + + /* USB_OC0# */ + Method(_L73, 0 , serialized) + { + Printf("USB Overcurrent Indicator"); + } } Scope (\_SB.PCI0) -- To view, visit https://review.coreboot.org/c/coreboot/+/47656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25fca6de44ce5c513fb6f7c4cfe46c5b7686fb20 Gerrit-Change-Number: 47656 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: Mic_Bias voltage changed to 2.9V for Earpods Mic
by Vani Ganji (Code Review) 07 Aug '23

07 Aug '23

Vani Ganji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35961 ) Change subject: Mic_Bias voltage changed to 2.9V for Earpods Mic ...................................................................... Mic_Bias voltage changed to 2.9V for Earpods Mic Earpods Mic is not working with 2.6Volts and it requires a volatge greater than 2.7Volts. BUG=b:134361881 Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Signed-off-by: Vani Ganji <vani.ganji(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35961/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..b42313f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -347,7 +347,7 @@ register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" + register "micbias_lvl" = "2900" register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Gerrit-Change-Number: 35961 Gerrit-PatchSet: 1 Gerrit-Owner: Vani Ganji <vani.ganji(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mainboard/intel/tgl: Customize PCH VR settings for better Sx power sa...
by Shreesh Chhabbi (Code Review) 07 Aug '23

07 Aug '23

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43992 to review the following change. Change subject: mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings ...................................................................... mainboard/intel/tgl: Customize PCH VR settings for better Sx power savings Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43992/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..1aa1f26 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -151,6 +151,20 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..169433b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -147,6 +147,20 @@ }, }" + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL | + FIVR_VOLTAGE_MIN_ACTIVE | + FIVR_VOLTAGE_MIN_RETENTION, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1250, + }" + device domain 0 on #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y -- To view, visit https://review.coreboot.org/c/coreboot/+/43992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic889d0952b75a636d2186d81fb679f74d50e7048 Gerrit-Change-Number: 43992 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

6 11

Change in coreboot[master]: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4
by Ravishankar Sarawadi (Code Review) 07 Aug '23

07 Aug '23

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44748 ) Change subject: [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 ...................................................................... [WIP]mb/volteer: Remove DQ/DQS mappings for LPDDR4 MRC v incorporates algorithm which finds the Dq mapping between CPU and DRAM by using CPGC to issue reads and and walking through setting each bit and reading it back through datatrainfeedback. Only LPDDR4 will be enabling this function at this time. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca --- M src/mainboard/google/volteer/variants/baseboard/memory.c M src/mainboard/google/volteer/variants/delbin/memory.c M src/mainboard/google/volteer/variants/halvor/memory.c M src/mainboard/google/volteer/variants/malefor/memory.c M src/mainboard/google/volteer/variants/terrador/memory.c M src/mainboard/google/volteer/variants/todor/memory.c M src/mainboard/google/volteer/variants/voxel/memory.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 9 files changed, 0 insertions(+), 565 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44748/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b..910916b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -5,54 +5,6 @@ #include <gpio.h> static const struct lpddr4x_cfg baseboard_lpddr4x_memcfg = { - /* DQ CPU<>DRAM map */ - .dq_map = { - [0] = { - { 0, 1, 2, 3, 4, 5, 6, 7, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 7, 2, 6, 3, 5, 1, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 10, 8, 9, 11, 15, 12, 14, 13, }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13, }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 3, 2, 1, 0, 4, 5, 6, 7, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8, }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8, }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11, }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13, }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/delbin/memory.c b/src/mainboard/google/volteer/variants/delbin/memory.c index 9d8ad40..1f93c38 100644 --- a/src/mainboard/google/volteer/variants/delbin/memory.c +++ b/src/mainboard/google/volteer/variants/delbin/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg delbin_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 2, 1, 0, 4, 5, 7, 6, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 11, 10, 9, 8 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 5, 3, 4, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 12, 10, 13, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 2, 3, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 9, 8 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 7, 0, 1, 6, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 13, 11, 12 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 4, 5, 2, 3, 7, 6, 0, 1, }, /* DDR4_DQ0[7:0] */ - { 12, 13, 15, 14, 11, 10, 8, 9 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 12, 13, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 7, 4, 5, 6, }, /* DDR6_DQ0[7:0] */ - { 15, 14, 13, 12, 8, 9, 10, 11 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 2, 4, 3, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 14, 15, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c index edbb681..cb0bbbae 100644 --- a/src/mainboard/google/volteer/variants/halvor/memory.c +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg halvor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ - { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ - { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ - { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ - { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ - { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ - { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ - { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c index 2c879e0..b1ade9e 100644 --- a/src/mainboard/google/volteer/variants/malefor/memory.c +++ b/src/mainboard/google/volteer/variants/malefor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg malefor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ - { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ - { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ - { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ - { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ - { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ - { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ - { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/terrador/memory.c b/src/mainboard/google/volteer/variants/terrador/memory.c index 7d95658..a8f5ea8 100644 --- a/src/mainboard/google/volteer/variants/terrador/memory.c +++ b/src/mainboard/google/volteer/variants/terrador/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg terrador_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c index c8b4ab4..e61f3b8 100644 --- a/src/mainboard/google/volteer/variants/todor/memory.c +++ b/src/mainboard/google/volteer/variants/todor/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg todor_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ - { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ - { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ - { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ - { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ - { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ - { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ - { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ - { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ - [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ - [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/mainboard/google/volteer/variants/voxel/memory.c b/src/mainboard/google/volteer/variants/voxel/memory.c index 40b1086..a028ab7 100644 --- a/src/mainboard/google/volteer/variants/voxel/memory.c +++ b/src/mainboard/google/volteer/variants/voxel/memory.c @@ -3,54 +3,6 @@ #include <baseboard/variants.h> static const struct lpddr4x_cfg voxel_memcfg = { - /* DQ byte map */ - .dq_map = { - [0] = { - { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ - { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ - }, - [1] = { - { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ - { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ - }, - [2] = { - { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ - { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ - }, - [3] = { - { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ - { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ - }, - [4] = { - { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ - { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ - }, - [5] = { - { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ - { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ - }, - [6] = { - { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ - { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ - }, - [7] = { - { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ - { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ - }, - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ - [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ - [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ - [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ - [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ - [5] = { 1, 0 }, /* DDR5_DQS[1:0] */ - [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ - [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ - }, - .ect = 1, /* Enable Early Command Training */ }; diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 4a52298..a9bf918 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -64,30 +64,6 @@ /* Board-specific memory configuration information */ struct lpddr4x_cfg { /* - * DQ CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[7-0]_DQ[1-0][7:0], where - * DDR[7-0] : LPDDR4x channel # - * DQ[1-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - - /* - * DQS CPU<>DRAM map: - * LPDDR4x memory interface has 2 DQS pairs(P/N) per channel. Thus, dqs_map is - * represented as DDR[7-0]_DQS[1:0], where - * DDR[7-0] : LPDDR4x channel # - * DQS[1-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dqs_map[LPDDR4X_CHANNELS][LPDDR4X_BYTES_PER_CHANNEL]; - /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable */ @@ -97,29 +73,6 @@ /* Board-specific memory configuration information for DDR4 memory variant */ struct mb_ddr4_cfg { /* - * DQ CPU<>DRAM map: - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits(1 - * byte). Thus, dq_map is represented as DDR[1-0]_DQ[7-0][7:0], where - * DDR[1-0] : DDR4 channel # - * DQ[7-0] : DQ # within the channel - * [7:0] : Bits within the DQ - * - * Index of the array represents DQ pin# on the CPU, whereas value in - * the array represents DQ pin# on the memory part. - */ - uint8_t dq_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL][BITS_PER_BYTE]; - /* - * DQS CPU<>DRAM map: - * DDR4 memory interface has 8 DQS pairs per channel. Thus, dqs_map is represented as - * DDR[1-0]_DQS[7-0], where - * DDR[1-0] : DDR4 channel # - * DQS[7-0] : DQS # within the channel - * - * Index of the array represents DQS pin# on the CPU, whereas value in - * the array represents DQS pin# on the memory part. - */ - uint8_t dqs_map[DDR4_CHANNELS][DDR4_BYTES_PER_CHANNEL]; - /* * Indicates whether memory is interleaved. * Set to 1 for an interleaved design, * set to 0 for non-interleaved design. diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 0c6f0b0..7093d3d 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -109,96 +109,6 @@ init_spd_upds(mem_cfg, channel, spd_dimm0, 0); } -static void init_dq_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, const uint8_t *dq_byte0, - const uint8_t *dq_byte1) -{ - uint8_t *dq_upd; - - switch (byte_pair) { - case 0: - dq_upd = mem_cfg->DqMapCpu2DramCh0; - break; - case 1: - dq_upd = mem_cfg->DqMapCpu2DramCh1; - break; - case 2: - dq_upd = mem_cfg->DqMapCpu2DramCh2; - break; - case 3: - dq_upd = mem_cfg->DqMapCpu2DramCh3; - break; - case 4: - dq_upd = mem_cfg->DqMapCpu2DramCh4; - break; - case 5: - dq_upd = mem_cfg->DqMapCpu2DramCh5; - break; - case 6: - dq_upd = mem_cfg->DqMapCpu2DramCh6; - break; - case 7: - dq_upd = mem_cfg->DqMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - if (dq_byte0 && dq_byte1) { - memcpy(dq_upd, dq_byte0, BITS_PER_BYTE); - memcpy(dq_upd + BITS_PER_BYTE, dq_byte1, BITS_PER_BYTE); - } else { - memset(dq_upd, 0, BITS_PER_BYTE * 2); - } -} - -static inline void init_dq_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dq_upds(mem_cfg, byte_pair, NULL, NULL); -} - -static void init_dqs_upds(FSP_M_CONFIG *mem_cfg, int byte_pair, uint8_t dqs_byte0, - uint8_t dqs_byte1) -{ - uint8_t *dqs_upd; - - switch (byte_pair) { - case 0: - dqs_upd = mem_cfg->DqsMapCpu2DramCh0; - break; - case 1: - dqs_upd = mem_cfg->DqsMapCpu2DramCh1; - break; - case 2: - dqs_upd = mem_cfg->DqsMapCpu2DramCh2; - break; - case 3: - dqs_upd = mem_cfg->DqsMapCpu2DramCh3; - break; - case 4: - dqs_upd = mem_cfg->DqsMapCpu2DramCh4; - break; - case 5: - dqs_upd = mem_cfg->DqsMapCpu2DramCh5; - break; - case 6: - dqs_upd = mem_cfg->DqsMapCpu2DramCh6; - break; - case 7: - dqs_upd = mem_cfg->DqsMapCpu2DramCh7; - break; - default: - die("Invalid byte_pair: %d\n", byte_pair); - } - - dqs_upd[0] = dqs_byte0; - dqs_upd[1] = dqs_byte1; -} - -static inline void init_dqs_upds_empty(FSP_M_CONFIG *mem_cfg, int byte_pair) -{ - init_dqs_upds(mem_cfg, byte_pair, 0, 0); -} - static void read_spd_from_cbfs(uint8_t index, uintptr_t *data, size_t *len) { struct region_device spd_rdev; @@ -252,51 +162,6 @@ else init_spd_upds_dimm0(mem_cfg, i, spd_data); } - - /* - * LPDDR4x memory interface has 2 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh2 --> dq_map[CHAN=2][0-1] - * DqMapCpu2DramCh3 --> dq_map[CHAN=3][0-1] - * DqMapCpu2DramCh4 --> dq_map[CHAN=4][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=5][0-1] - * DqMapCpu2DramCh6 --> dq_map[CHAN=6][0-1] - * DqMapCpu2DramCh7 --> dq_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dq_upds_empty(mem_cfg, i); - else - init_dq_upds(mem_cfg, i, board_cfg->dq_map[i][0], - board_cfg->dq_map[i][1]); - } - - /* - * LPDDR4x memory interface has 2 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=2][0-1] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=3][0-1] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=4][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=5][0-1] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=6][0-1] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=7][0-1] - */ - for (i = 0; i < LPDDR4X_CHANNELS; i++) { - if (LPDDR4X_CHANNEL_UNPOPULATED(i, half_populated)) - init_dqs_upds_empty(mem_cfg, i); - else - init_dqs_upds(mem_cfg, i, board_cfg->dqs_map[i][0], - board_cfg->dqs_map[i][1]); - } } static void read_sodimm_spd(const struct spd_info *info, struct spd_block *blk) @@ -363,7 +228,6 @@ uintptr_t spd_dimm1 = 0; struct spd_block spd_sodimm_blk; unsigned int i; - unsigned int index = 0; /* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; @@ -388,52 +252,6 @@ half_populated, &spd_dimm0, &spd_dimm1); init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); } - - /* - * DDR4 memory interface has 8 DQs per channel. Each DQ consists of 8 bits (1 - * byte). However, FSP UPDs for DQ Map expect a DQ pair (i.e. mapping for 2 bytes) in - * each UPD. - * - * Thus, init_dq_upds() needs to be called for every dq pair of each channel. - * DqMapCpu2DramCh0 --> dq_map[CHAN=0][0-1] - * DqMapCpu2DramCh1 --> dq_map[CHAN=0][2-3] - * DqMapCpu2DramCh2 --> dq_map[CHAN=0][4-5] - * DqMapCpu2DramCh3 --> dq_map[CHAN=0][6-7] - * DqMapCpu2DramCh4 --> dq_map[CHAN=1][0-1] - * DqMapCpu2DramCh5 --> dq_map[CHAN=1][2-3] - * DqMapCpu2DramCh6 --> dq_map[CHAN=1][4-5] - * DqMapCpu2DramCh7 --> dq_map[CHAN=1][6-7] - */ - - /* - * DDR4 memory interface has 8 DQS pairs per channel. FSP UPDs for DQS Map expect a - * pair in each UPD. - * - * Thus, init_dqs_upds() needs to be called for every dqs pair of each channel. - * DqsMapCpu2DramCh0 --> dqs_map[CHAN=0][0-1] - * DqsMapCpu2DramCh1 --> dqs_map[CHAN=0][2-3] - * DqsMapCpu2DramCh2 --> dqs_map[CHAN=0][4-5] - * DqsMapCpu2DramCh3 --> dqs_map[CHAN=0][6-7] - * DqsMapCpu2DramCh4 --> dqs_map[CHAN=1][0-1] - * DqsMapCpu2DramCh5 --> dqs_map[CHAN=1][2-3] - * DqsMapCpu2DramCh6 --> dqs_map[CHAN=1][4-5] - * DqsMapCpu2DramCh7 --> dqs_map[CHAN=1][6-7] - */ - - for (i = 0; i < DDR4_CHANNELS; i++) { - for (int b = 0; b < DDR4_BYTES_PER_CHANNEL; b += 2) { - if (half_populated && (i == 1)) { - init_dq_upds_empty(mem_cfg, index); - init_dqs_upds_empty(mem_cfg, index); - } else { - init_dq_upds(mem_cfg, index, board_cfg->dq_map[i][b], - board_cfg->dq_map[i][b+1]); - init_dqs_upds(mem_cfg, index, board_cfg->dqs_map[i][b], - board_cfg->dqs_map[i][b+1]); - } - index++; - } - } } void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/44748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70da3d482385fe6b1ccf071af8d8bd8e44d898ca Gerrit-Change-Number: 44748 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

7 24

Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review) 07 Aug '23

07 Aug '23

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

9 29

← Newer
1
...
31
32
33
34
35
36
37
...
68
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2022