Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43395 )
Change subject: cpu/x86/16bit/entry16.inc: Stop PBET timer on Boot Guard platforms
......................................................................
cpu/x86/16bit/entry16.inc: Stop PBET timer on Boot Guard platforms
PBET timer has to be stopped before APs are launched and initialized.
Otherwise the platform will reset. The PBET expiration time may be very
low so stop timer as quickly as possible. The expiration time is defined
in Boot Guard manifests.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I545a36d60597fe37a30b8207336ae7fa7831674d
---
M src/cpu/x86/16bit/entry16.inc
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/43395/1
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index babed02..c555c5c 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,6 +29,7 @@
#include <cpu/x86/post_code.h>
#define BOOTGUARD_SACM_INFO 0x13a
+#define BOOTGUARD_PBEC 0x139
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
@@ -118,6 +119,14 @@
andl $0x7FFAFFD1, %ebx /* PG,AM,WP,NE,TS,EM,MP = 0 */
orl $0x60000001, %ebx /* CD, NW, PE = 1 */
#if CONFIG(INTEL_BOOTGUARD)
+ /*
+ * Stop PBET timer. It is recommended to stop the PBET timer
+ * regardless of Boot Guard status.
+ */
+ movl $BOOTGUARD_PBEC, %ecx
+ movl $0, %edx
+ movl $1, %eax
+ wrmsr
/* DO NOT disable cache if Intel BootGuard is supported */
movl $BOOTGUARD_SACM_INFO, %ecx
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I545a36d60597fe37a30b8207336ae7fa7831674d
Gerrit-Change-Number: 43395
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-MessageType: newchange
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43401 )
Change subject: program layout: align to 64 bytes when Boot Guard is enabled
......................................................................
program layout: align to 64 bytes when Boot Guard is enabled
FIT entries for IBB segmnets have 64 byte granularity. Enforce the
64 bytes alignment on all programs and FIT table to ensure the
entires for IBB will be added correctly.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I3ce09e24d716fe9845104205bc934bd2a0efc9cb
---
M src/arch/x86/memlayout.ld
M src/cpu/intel/fit/fit.S
M src/lib/program.ld
3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/43401/1
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index 3659cc9..605ed24 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -47,3 +47,8 @@
#include <cpu/intel/fit/fit.ld>
#endif
#endif /* ENV_BOOTBLOCK */
+
+/* Each program stage needs to be 64 bytes aligned to be added as FIT entry */
+#if CONFIG_INTEL_BOOTGUARD
+. = ALIGN(64);
+#endif
diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S
index 3b7396c..037918a 100644
--- a/src/cpu/intel/fit/fit.S
+++ b/src/cpu/intel/fit/fit.S
@@ -9,7 +9,15 @@
.previous
.section .text
+#if CONFIG(INTEL_BOOTGUARD)
+/*
+ * FIT must be excluded from IBB with BootGuard. As the IBB segments have 64
+ * byte granularity, align the FIT to 64 bytes.
+ */
+.align 64
+#else
.align 16
+#endif
.global fit_table
.global fit_table_end
fit_table:
@@ -28,5 +36,12 @@
/* Checksum byte - must add to zero. */
.byte 0x7d
.fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16
+#if CONFIG(INTEL_BOOTGUARD)
+/*
+ * Just in case the FIT does not end on 64 byte aligned address, maintain the
+ * 64 byte boundaries of IBB segments.
+ */
+.align 64
+#endif
fit_table_end:
.previous
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 88a3126..ee105e3 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -48,6 +48,10 @@
*(.rodata);
*(.rodata.*);
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
+#if CONFIG_INTEL_BOOTGUARD
+/* Each program stage needs to be 64 bytes aligned to be added as FIT entry */
+ . = ALIGN(64);
+#endif
_etext = .;
} : to_load
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3ce09e24d716fe9845104205bc934bd2a0efc9cb
Gerrit-Change-Number: 43401
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44262 )
Change subject: soc/intel/tigerlake: move mainboard_silicon_init_params
......................................................................
soc/intel/tigerlake: move mainboard_silicon_init_params
This patch arranges mainboard_silicon_init_params before fetching
any config variables from devicetree. This would allow the variant
specific devicetree overrides to get consumed so that FSP UPD
parameters are initialized properly before SiliconInit.
BUG=b:158573805
TEST=Test that UPD values are set properly with variant specific
overrides of config's .
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Change-Id: Idfce528efa7806e292071e092fb129b53a94a145
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44262/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index a61a025..5178d91 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -107,6 +107,8 @@
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ mainboard_silicon_init_params(params);
+
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable;
cpu_id = cpu_get_cpuid();
@@ -311,7 +313,6 @@
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
params->EnableMultiPhaseSiliconInit = 1;
- mainboard_silicon_init_params(params);
}
/*
--
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Gerrit-Change-Id: Idfce528efa7806e292071e092fb129b53a94a145
Gerrit-Change-Number: 44262
Gerrit-PatchSet: 1
Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-MessageType: newchange
ky0ko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44845 )
Change subject: mtrr.h: refine _POW2_MASK
......................................................................
mtrr.h: refine _POW2_MASK
this patch adjusts _POW2_MASK to work with rom sizes between 64KiB
and 512MiB, additionally fixing incorrectness for sizes 128MiB and
above that previously were present.
Change-Id: I0272c0c43cba44f6fbfb5dc539509b4ed9b92e75
Signed-off-by: ky0ko <ky0ko(a)disroot.org>
---
M src/include/cpu/x86/mtrr.h
1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44845/1
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 42964b0..fd4159d 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -176,9 +176,11 @@
#endif /* !defined(__ASSEMBLER__) */
/* Align up/down to next power of 2, suitable for assembler
- too. Range of result 256kB to 128MB is good enough here. */
+ too. Range works from 64kB to 512MB. */
#define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \
- (x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
+ (x>>6)|(x>>7)|(x>>8)|(x>>9)|(x>>10)| \
+ (x>>11)|(x>>12)|(x>>13)|((1<<16)-1))
+
#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
#define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x))
--
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Gerrit-Change-Number: 44845
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Gerrit-Owner: ky0ko <ky0ko(a)disroot.org>
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