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Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N
......................................................................
Patch Set 10: Code-Review+2
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Change subject: soc/qualcomm/common: Fix bugs introduced with CB:59195
......................................................................
Patch Set 6:
(1 comment)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/3f892bcc_ec84bc92
PS5, Line 30: uint64_t *
> Is said "this cast is unnecessary". I did not say "please change this to a uint64_t* cast". […]
hi julius,
As you suggested, if assign te->blob_address without type casting i am getting below error:
src/soc/qualcomm/common/qclib.c: In function 'write_mem_chip_information':
src/soc/qualcomm/common/qclib.c:30:31: error: assignment to 'void *' from 'uint64_t' {aka 'long long unsigned int'} makes pointer from integer without a cast [-Werror=int-conversion]
30 | mem_chip_addr = te->blob_address;
as per the above error i have mentioned type casting with uint64_t.
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Hello build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63419
to look at the new patch set (#9).
Change subject: Kconfig: Set better defaults for building romstage
......................................................................
Kconfig: Set better defaults for building romstage
On x86 there is generally no reason to have a separate romstage unless
VBOOT is used.
Change-Id: I4c53b6fa7a3e66415c5b1c539918a6c1cd8defa1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/soc/intel/apollolake/Kconfig
2 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63419/9
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Change subject: Allow to build romstage sources inside the bootblock
......................................................................
Patch Set 15:
(1 comment)
File src/include/rules.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145652):
https://review.coreboot.org/c/coreboot/+/55068/comment/02b8332b_f35e2c96
PS15, Line 313: #define ENV_FIRST_CBMEM_STAGE (CONFIG(SEPARATE_ROMSTAGE) ? ENV_ROMSTAGE : ENV_BOOTBLOCK)
line over 96 characters
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Change subject: soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/apollolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/62889/comment/f2998593_e124c151
PS2, Line 236: GPU_PRIMARY_PCI
> Sounds great! Thanks
I have now tested this patch on a APL CRB and I was able use the external graphic as intended with 'ONBOARD_VGA_IS_PRIMARY' not set. So to me both, internal and external graphic works with this change.
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Hello build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: Kconfig: Set better defaults for building romstage
......................................................................
Kconfig: Set better defaults for building romstage
On x86 there is generally no reason to have a separate romstage unless
VBOOT is used.
Change-Id: I4c53b6fa7a3e66415c5b1c539918a6c1cd8defa1
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---
M src/Kconfig
M src/soc/intel/apollolake/Kconfig
2 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63419/8
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I'd like you to reexamine a change. Please visit
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Change subject: arch/x86: Add a common romstage entry
......................................................................
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
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A src/arch/x86/romstage.c
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A src/include/romstage_common.h
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M src/soc/example/min86/romstage.c
10 files changed, 48 insertions(+), 55 deletions(-)
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Change subject: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63339/comment/0340b14b_715775ba
PS6, Line 11: stepping
> KConfig indicates the change is meant for A0. Since minor comment, I'm ignoring it.
I don't understand if we have any rule in coreboot code review that says:
"Since minor comment, I'm ignoring it"
Note: updating commit msg won't remove +2 vote if you are concerned.
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Change subject: mb/intel/adlrvp: Disable PM Timer for ADL-N
......................................................................
Removed Code-Review+2 by Meera Ravindranath <meera.ravindranath(a)intel.com>
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Change subject: mb/intel/adlrvp: Disable PM Timer for ADL-N
......................................................................
Patch Set 3: Code-Review+2
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