coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/var/nereid: Enable pen garage
by Patrick Georgi (Code Review) 07 Apr '22

07 Apr '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63370 ) Change subject: mb/google/brya/var/nereid: Enable pen garage ...................................................................... mb/google/brya/var/nereid: Enable pen garage BUG=None TEST=evtest works: Select the device event number [0-14]: 9 Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153020.275201, -------------- SYN_REPORT ------------ Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153025.848689, -------------- SYN_REPORT ------------ Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649153028.383195, -------------- SYN_REPORT ------------ Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: time 1649153080.869155, -------------- SYN_REPORT ------------ Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sam McNally <sammc(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/nereid/overridetree.cb 2 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved Sam McNally: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 4be2014..79320fd 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -92,6 +92,7 @@ bool "-> Nereid" select ALDERLAKE_CONFIGURE_DESCRIPTOR select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS config BOARD_GOOGLE_PRIMUS bool "-> Primus" diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 71987ff..2ec605f36 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -37,6 +37,18 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end device ref i2c3 on chip drivers/i2c/generic 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Gerrit-Change-Number: 63370 Gerrit-PatchSet: 4 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/lint/checkpatch.pl: Update lines related to max_line_length
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63439 ) Change subject: util/lint/checkpatch.pl: Update lines related to max_line_length ...................................................................... util/lint/checkpatch.pl: Update lines related to max_line_length Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c --- M util/lint/checkpatch.pl 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63439/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 6a9c345..4151e82 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -56,7 +56,7 @@ my @exclude = (); #coreboot my $help = 0; my $configuration_file = ".checkpatch.conf"; -my $max_line_length = 80; +my $max_line_length = 100; my $ignore_perl_version = 0; my $minimum_perl_version = 5.10.0; my $min_conf_desc_length = 4; @@ -111,7 +111,9 @@ --ignore TYPE(,TYPE2...) ignore various comma separated message types --exclude DIR(,DIR22...) exclude directories --show-types show the specific message type in the output - --max-line-length=n set the maximum line length, if exceeded, warn + --max-line-length=n set the maximum line length, (default $max_line_length) + if exceeded, warn on patches + requires --strict for use with --file --min-conf-desc-length=n set the min description length, if shorter, warn --tab-size=n set the number of spaces for tab (default $tabsize) --root=PATH PATH to the kernel tree root @@ -3196,8 +3198,10 @@ if ($msg_type ne "" && (show_type("LONG_LINE") || show_type($msg_type))) { - WARN($msg_type, - "line over $max_line_length characters\n" . $herecurr); + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}($msg_type, + "line length of $length exceeds $max_line_length columns\n" . $herecurr); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c Gerrit-Change-Number: 63439 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/nereid: Configure descriptor for either Type-C or ...
by Patrick Georgi (Code Review) 07 Apr '22

07 Apr '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63366 ) Change subject: mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI ...................................................................... mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI Some bytes in the descriptor need to be set differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the descriptor at runtime based on fw_config. This is a temporary workaround while we find a better solution. The byte values were determined by changing the following CSE strap and comparing the generated descriptors: Type-C: TypeCPort2Config = "No Thunderbolt" HDMI: TypeCPort2Config = "DP Fixed Connection" The default value before updating the descriptor is Type-C, but this was chosen arbitrarily. BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly. Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc(a)google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/bootblock.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/nereid/Makefile.inc M src/mainboard/google/brya/variants/nereid/variant.c 5 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3126d28..4be2014 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -90,6 +90,7 @@ config BOARD_GOOGLE_NEREID bool "-> Nereid" + select ALDERLAKE_CONFIGURE_DESCRIPTOR select BOARD_GOOGLE_BASEBOARD_NISSA config BOARD_GOOGLE_PRIMUS diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index 1815615..c24e959 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -10,3 +10,10 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); } + +void bootblock_mainboard_init(void) +{ + variant_update_descriptor(); +} + +void __weak variant_update_descriptor(void) {} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 8c79a8a..baf0597 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -34,6 +34,8 @@ /* Modify devictree settings during ramstage */ void variant_devtree_update(void); +void variant_update_descriptor(void); + struct cpu_power_limits { uint16_t mchid; u8 cpu_tdp; diff --git a/src/mainboard/google/brya/variants/nereid/Makefile.inc b/src/mainboard/google/brya/variants/nereid/Makefile.inc index 2e8157e..16c9748 100644 --- a/src/mainboard/google/brya/variants/nereid/Makefile.inc +++ b/src/mainboard/google/brya/variants/nereid/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +bootblock-y += variant.c romstage-y += gpio.c romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/nereid/variant.c b/src/mainboard/google/brya/variants/nereid/variant.c index 967fc9a..74afb27 100644 --- a/src/mainboard/google/brya/variants/nereid/variant.c +++ b/src/mainboard/google/brya/variants/nereid/variant.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <baseboard/variants.h> +#include <console/console.h> #include <drivers/intel/gma/opregion.h> #include <fw_config.h> +#include <soc/bootblock.h> const char *mainboard_vbt_filename(void) { @@ -10,3 +13,30 @@ return "vbt.bin"; } + +void variant_update_descriptor(void) +{ + /* TypeCPort2Config = "No Thunderbolt" */ + struct descriptor_byte typec_bytes[] = { + { 0xc76, 0xb7 }, + { 0xc77, 0xb6 }, + { 0xc7c, 0xee }, + { 0xca0, 0x0c }, + }; + + /* TypeCPort2Config = "DP Fixed Connection" */ + struct descriptor_byte hdmi_bytes[] = { + { 0xc76, 0x75 }, + { 0xc77, 0xc4 }, + { 0xc7c, 0x1e }, + { 0xca0, 0x0e }, + }; + + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_HDMI))) { + printk(BIOS_INFO, "Configuring descriptor for HDMI\n"); + configure_descriptor(hdmi_bytes, ARRAY_SIZE(hdmi_bytes)); + } else { + printk(BIOS_INFO, "Configuring descriptor for Type-C\n"); + configure_descriptor(typec_bytes, ARRAY_SIZE(typec_bytes)); + } +} 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Gerrit-Change-Number: 63366 Gerrit-PatchSet: 13 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add support to update descriptor at runtime
by Patrick Georgi (Code Review) 07 Apr '22

07 Apr '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63365 ) Change subject: soc/intel/alderlake: Add support to update descriptor at runtime ...................................................................... soc/intel/alderlake: Add support to update descriptor at runtime On nereid, we need to update the descriptor based on fw_config (see the follow-up patch), so add support to update the descriptor at runtime. This is a temporary workaround while we find a better solution. This is basically adding back the configure_pmc_descriptor() function removed in CB:63339, just making it generic and allowing it to update multiple bytes at once. BUG=b:226848617 TEST=With the following patch, Type-C and HDMI work on nereid. Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63365 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sam McNally <sammc(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/bootblock/update_descriptor.c M src/soc/intel/alderlake/include/soc/bootblock.h 4 files changed, 107 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b2f90f8..d3c52944 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -112,6 +112,13 @@ select UDK_202005_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM +config ALDERLAKE_CONFIGURE_DESCRIPTOR + bool + help + Select this if the descriptor needs to be updated at runtime. This + can only be done if the descriptor region is writable, and should only + be used as a temporary workaround. + config ALDERLAKE_CAR_ENHANCED_NEM bool default y if !INTEL_CAR_NEM diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index b3235cd..a03c42a 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += p2sb.c +bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c romstage-y += espi.c romstage-y += gpio.c diff --git a/src/soc/intel/alderlake/bootblock/update_descriptor.c b/src/soc/intel/alderlake/bootblock/update_descriptor.c new file mode 100644 index 0000000..436825d --- /dev/null +++ b/src/soc/intel/alderlake/bootblock/update_descriptor.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/cpu.h> +#include <arch/mmio.h> +#include <cf9_reset.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/intel/cpu_ids.h> +#include <fmap.h> +#include <intelblocks/pmclib.h> +#include <soc/bootblock.h> +#include <types.h> + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 + +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A + +/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ +static bool is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_ERR, "Flash Descriptor is not valid\n"); + return 0; + } + + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + + return 1; +} + +void configure_descriptor(struct descriptor_byte *bytes, size_t num) +{ + uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ]; + struct region_device desc_rdev; + bool update_required = false; + + if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", CONFIG_SI_DESC_REGION); + return; + } + + if (rdev_readat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) != + CONFIG_SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return; + } + + if (!is_descriptor_writeable(si_desc_buf)) + return; + + for (size_t i = 0; i < num; i++) { + size_t offset = bytes[i].offset; + uint8_t desired_value = bytes[i].desired_value; + printk(BIOS_DEBUG, "Current value of Descriptor byte 0x%lx: 0x%x\n", + offset, si_desc_buf[offset]); + if (si_desc_buf[offset] != desired_value) { + update_required = true; + si_desc_buf[offset] = desired_value; + } + } + + if (!update_required) { + printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); + return; + } + + if (rdev_eraseat(&desc_rdev, 0, CONFIG_SI_DESC_REGION_SZ) != CONFIG_SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) + != CONFIG_SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + return; + } + + printk(BIOS_DEBUG, "Update of Descriptor successful, trigger GLOBAL RESET\n"); + + pmc_global_reset_enable(true); + do_full_reset(); + die("Failed to trigger GLOBAL RESET\n"); +} diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index ce2e42e..ba4d1c2 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -9,6 +9,11 @@ #error "Please select exactly one PCH type" #endif +struct descriptor_byte { + size_t offset; + uint8_t desired_value; +}; + /* Bootblock pre console init programming */ void bootblock_pch_early_init(void); @@ -17,4 +22,6 @@ void pch_early_iorange_init(void); void report_platform_info(void); +void configure_descriptor(struct descriptor_byte *bytes, size_t num); + #endif 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe Gerrit-Change-Number: 63365 Gerrit-PatchSet: 10 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Don't declare tools directory twice
by Sean Rhodes (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Sean Rhodes, Martin Roth, Matt DeVillier, Stefan Reinauer. Hello build bot (Jenkins), Martin Roth, Matt DeVillier, Stefan Reinauer, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63180 to look at the new patch set (#3). Change subject: payloads/tianocore: Don't declare tools directory twice ...................................................................... payloads/tianocore: Don't declare tools directory twice EDK_TOOLS_PATH is set on lines 85 and 137. Remove the instance on 85. edk2 still builds correctly. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I0c837f14693941afec194b140c93d786ea784e53 --- M payloads/external/tianocore/Makefile 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/63180/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c837f14693941afec194b140c93d786ea784e53 Gerrit-Change-Number: 63180 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig
by Patrick Georgi (Code Review) 07 Apr '22

07 Apr '22

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63339 ) Change subject: soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig ...................................................................... soc/intel/alderlake: Remove ALDERLAKE_A0_CONFIG_PMC_DESCRIPTOR Kconfig The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR code which updates PMC descriptor for an intermediate ADL-P SoC stepping A0. Since intermediate ADL-P SoC is no longer supported and no board is selecting the Kconfig, so remove the code that updates PMC descriptor. TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63339 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/bootblock.c D src/soc/intel/alderlake/bootblock/pmc_descriptor.c M src/soc/intel/alderlake/include/soc/bootblock.h 5 files changed, 0 insertions(+), 103 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 6b0a27a..b2f90f8 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -112,15 +112,6 @@ select UDK_202005_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM -config ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR - bool - help - Alder Lake stepping A0 needs a different value for a PMC setting in - the IFD. When this option is selected, coreboot will update the IFD - value at runtime, which allows using an IFD with the new value with - any CPU stepping. To apply this workaround, the IFD region needs to - be writable by the host. - config ALDERLAKE_CAR_ENHANCED_NEM bool default y if !INTEL_CAR_NEM diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 16784aa..b3235cd 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += p2sb.c -bootblock-$(CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR) += bootblock/pmc_descriptor.c romstage-y += espi.c romstage-y += gpio.c diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index e209ae2..b8086a4 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -25,9 +25,6 @@ void bootblock_soc_init(void) { - if (CONFIG(ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR)) - configure_pmc_descriptor(); - report_platform_info(); bootblock_pch_init(); diff --git a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c b/src/soc/intel/alderlake/bootblock/pmc_descriptor.c deleted file mode 100644 index 14a9dcb..0000000 --- a/src/soc/intel/alderlake/bootblock/pmc_descriptor.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <arch/cpu.h> -#include <arch/mmio.h> -#include <cf9_reset.h> -#include <commonlib/region.h> -#include <console/console.h> -#include <cpu/intel/cpu_ids.h> -#include <fmap.h> -#include <intelblocks/pmclib.h> -#include <soc/bootblock.h> -#include <types.h> - -#define PMC_DESC_7_BYTE3 0xc32 - -/* Flash Master 1 : HOST/BIOS */ -#define FLMSTR1 0x80 - -/* Flash signature Offset */ -#define FLASH_SIGN_OFFSET 0x10 -#define FLMSTR_WR_SHIFT_V2 20 -#define FLASH_VAL_SIGN 0xFF0A55A - -/* It checks whether host(Flash Master 1) has write access to the Descriptor Region or not */ -static int is_descriptor_writeable(uint8_t *desc) -{ - /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { - printk(BIOS_DEBUG, "Flash Descriptor is not valid\n"); - return 0; - } - - /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { - printk(BIOS_DEBUG, "Host doesn't have write access to Descriptor Region\n"); - return 0; - } - - return 1; -} - -/* It updates PMC Descriptor in the Descriptor Region */ -void configure_pmc_descriptor(void) -{ - uint8_t si_desc_buf[CONFIG_SI_DESC_REGION_SZ]; - struct region_device desc_rdev; - - if (cpu_get_cpuid() != CPUID_ALDERLAKE_J0) - return; - - if (fmap_locate_area_as_rdev_rw(CONFIG_SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", CONFIG_SI_DESC_REGION); - return; - } - - if (rdev_readat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) != - CONFIG_SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); - return; - } - - if (!is_descriptor_writeable(si_desc_buf)) - return; - - if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) { - printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); - return; - } - - si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; - - if (rdev_eraseat(&desc_rdev, 0, CONFIG_SI_DESC_REGION_SZ) != CONFIG_SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); - return; - } - - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, CONFIG_SI_DESC_REGION_SZ) - != CONFIG_SI_DESC_REGION_SZ) { - printk(BIOS_ERR, "Failed to update Descriptor Region\n"); - return; - } - - printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); - - pmc_global_reset_enable(true); - do_full_reset(); - die("Failed to trigger GLOBAL RESET\n"); -} diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index e989bdd..ce2e42e 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -17,6 +17,4 @@ void pch_early_iorange_init(void); void report_platform_info(void); -void configure_pmc_descriptor(void); - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7 Gerrit-Change-Number: 63339 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/lint/checkpatch.pl: Update lines related to tabsize
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63438 ) Change subject: util/lint/checkpatch.pl: Update lines related to tabsize ...................................................................... util/lint/checkpatch.pl: Update lines related to tabsize Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b --- M util/lint/checkpatch.pl 1 file changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/63438/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 65c2b5b..6a9c345 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -113,6 +113,7 @@ --show-types show the specific message type in the output --max-line-length=n set the maximum line length, if exceeded, warn --min-conf-desc-length=n set the min description length, if shorter, warn + --tab-size=n set the number of spaces for tab (default $tabsize) --root=PATH PATH to the kernel tree root --no-summary suppress the per-file summary --mailback only produce a report in case of warnings/errors @@ -308,6 +309,7 @@ 'list-types!' => \$list_types, 'max-line-length=i' => \$max_line_length, 'min-conf-desc-length=i' => \$min_conf_desc_length, + 'tab-size=i' => \$tabsize, 'root=s' => \$root, 'summary!' => \$summary, 'mailback!' => \$mailback, @@ -387,17 +389,8 @@ push(@ARGV, '-'); } -if ($color =~ /^[01]$/) { - $color = !$color; -} elsif ($color =~ /^always$/i) { - $color = 1; -} elsif ($color =~ /^never$/i) { - $color = 0; -} elsif ($color =~ /^auto$/i) { - $color = (-t STDOUT); -} else { - die "Invalid color mode: $color\n"; -} +# skip TAB size 1 to avoid additional checks on $tabsize - 1 +die "$P: Invalid TAB size: $tabsize\n" if ($tabsize < 2); sub hash_save_array_words { my ($hashRef, $arrayRef) = @_; -- To view, visit https://review.coreboot.org/c/coreboot/+/63438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b Gerrit-Change-Number: 63438 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: *util/lint/checkpatch.pl: Update lines related to verbosity
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63437 ) Change subject: *util/lint/checkpatch.pl: Update lines related to verbosity ...................................................................... *util/lint/checkpatch.pl: Update lines related to verbosity Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa --- M util/lint/checkpatch.pl 1 file changed, 95 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/63437/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 0bb6844..65c2b5b 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -65,7 +65,8 @@ my $codespellfile = "/usr/share/codespell/dictionary.txt"; my $user_codespellfile = ""; my $conststructsfile = "$D/const_structs.checkpatch"; -my $typedefsfile = ""; +my $docsfile = "$D/../Documentation/dev-tools/checkpatch.rst"; +my $typedefsfile; my $color = "auto"; my $allow_c99_comments = 1; my $git_command ='git'; # coreboot @@ -86,6 +87,7 @@ Options: -q, --quiet quiet + -v, --verbose verbose mode --no-tree run without a kernel tree --no-signoff do not check for 'Signed-off-by' line --patch treat FILE as patchfile (default) @@ -162,15 +164,51 @@ my $text = <$script>; close($script); - my @types = (); + my %types = (); # Also catch when type or level is passed through a variable - for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { - push (@types, $_); + while ($text =~ /(?:(\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { + if (defined($1)) { + if (exists($types{$2})) { + $types{$2} .= ",$1" if ($types{$2} ne $1); + } else { + $types{$2} = $1; + } + } else { + $types{$2} = "UNDETERMINED"; + } } - @types = sort(uniq(@types)); + print("#\tMessage type\n\n"); - foreach my $type (@types) { + if ($color) { + print(" ( Color coding: "); + print(RED . "ERROR" . RESET); + print(" | "); + print(YELLOW . "WARNING" . RESET); + print(" | "); + print(GREEN . "CHECK" . RESET); + print(" | "); + print("Multiple levels / Undetermined"); + print(" )\n\n"); + } + + foreach my $type (sort keys %types) { + my $orig_type = $type; + if ($color) { + my $level = $types{$type}; + if ($level eq "ERROR") { + $type = RED . $type . RESET; + } elsif ($level eq "WARN") { + $type = YELLOW . $type . RESET; + } elsif ($level eq "CHK") { + $type = GREEN . $type . RESET; + } + } print(++$count . "\t" . $type . "\n"); + if ($verbose && exists($verbose_messages{$orig_type})) { + my $message = $verbose_messages{$orig_type}; + $message =~ s/\n/\n\t/g; + print("\t" . $message . "\n\n"); + } } exit($exitcode); @@ -202,6 +240,46 @@ unshift(@ARGV, @conf_args) if @conf_args; } +sub load_docs { + open(my $docs, '<', "$docsfile") + or warn "$P: Can't read the documentation file $docsfile $!\n"; + + my $type = ''; + my $desc = ''; + my $in_desc = 0; + + while (<$docs>) { + chomp; + my $line = $_; + $line =~ s/\s+$//; + + if ($line =~ /^\s*\*\*(.+)\*\*$/) { + if ($desc ne '') { + $verbose_messages{$type} = trim($desc); + } + $type = $1; + $desc = ''; + $in_desc = 1; + } elsif ($in_desc) { + if ($line =~ /^(?:\s{4,}|$)/) { + $line =~ s/^\s{4}//; + $desc .= $line; + $desc .= "\n"; + } else { + $verbose_messages{$type} = trim($desc); + $type = ''; + $desc = ''; + $in_desc = 0; + } + } + } + + if ($desc ne '') { + $verbose_messages{$type} = trim($desc); + } + close($docs); +} + # Perl's Getopt::Long allows options to take optional arguments after a space. # Prevent --color by itself from consuming other arguments foreach (@ARGV) { @@ -212,6 +290,7 @@ GetOptions( 'q|quiet+' => \$quiet, + 'v|verbose!' => \$verbose, 'tree!' => \$tree, 'signoff!' => \$chk_signoff, 'patch!' => \$chk_patch, @@ -2056,7 +2135,16 @@ splice(@lines, 1, 1); $output = join("\n", @lines); } - $output = (split('\n', $output))[0] . "\n" if ($terse); + + if ($terse) { + $output = (split('\n', $output))[0] . "\n"; + } + + if ($verbose && exists($verbose_messages{$type}) && + !exists($verbose_emitted{$type})) { + $output .= $verbose_messages{$type} . "\n\n"; + $verbose_emitted{$type} = 1; + } push(our @report, $output); -- To view, visit https://review.coreboot.org/c/coreboot/+/63437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa Gerrit-Change-Number: 63437 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/nereid: Enable pen garage
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Sridhar Siricilla. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63370 ) Change subject: mb/google/brya/var/nereid: Enable pen garage ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1 Gerrit-Change-Number: 63370 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 08:03:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/nereid: Configure descriptor for either Type-C or ...
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sridhar Siricilla. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63366 ) Change subject: mb/google/brya/var/nereid: Configure descriptor for either Type-C or HDMI ...................................................................... Patch Set 12: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Gerrit-Change-Number: 63366 Gerrit-PatchSet: 12 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 08:02:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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