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Change subject: util/intelp2m: Add support for Alder Lake macro generation
......................................................................
Patch Set 2:
(1 comment)
File util/intelp2m/description.md:
https://review.coreboot.org/c/coreboot/+/63403/comment/5e737b4c_8d8b9015
PS1, Line 39: AlderLake-H
> Hmmm, if "cnl" works for both PCH-H and PCH-LP, I don't see why it would be necessary to handle ADL […]
Upon second thought, this is correct. Changed all instances of `ADL-H` to `ADL`
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Hello build bot (Jenkins), Michał Żygowski, Maxim Polyakov, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63403
to look at the new patch set (#3).
Change subject: util/intelp2m: Add support for Alder Lake macro generation
......................................................................
util/intelp2m: Add support for Alder Lake macro generation
Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.
TEST=Generate GPIO macros for MSI PRO Z690-A
Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/intelp2m/config/config.go
M util/intelp2m/description.md
A util/intelp2m/gpio_adl_h.h
M util/intelp2m/main.go
M util/intelp2m/parser/parser.go
A util/intelp2m/platforms/adl/macro.go
A util/intelp2m/platforms/adl/template.go
7 files changed, 146 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63403/3
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63139 )
Change subject: Revert "soc/intel/alderlake: Use Kconfigs for Descriptor Region"
......................................................................
Patch Set 4: Verified+1
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Change subject: util/intelp2m: Add support for Alder Lake H macro generation
......................................................................
Patch Set 2:
(2 comments)
File util/intelp2m/description.md:
https://review.coreboot.org/c/coreboot/+/63403/comment/8d5b681a_d461100c
PS1, Line 39: AlderLake-H
> From a quick look at Intel docs #618659 and #627075 The GPIO functions are different, the communiti […]
Hmmm, if "cnl" works for both PCH-H and PCH-LP, I don't see why it would be necessary to handle ADL PCH-H separately from ADL PCH-LP.
File util/intelp2m/platforms/adlh/macro.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/1b9402b8_07d0b910
PS2, Line 20: MAX_DW_NUM = common.MAX_DW_NUM
According to coreboot code, ADL GPIOs have 4 DW registers
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Change subject: lib/hardwaremain.c: Move creating ACPI structs to bootstate hooks
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/vendorcode/google/chromeos/gnvs.c:
https://review.coreboot.org/c/coreboot/+/63414/comment/9dc8aad8_76ed84df
PS3, Line 61: BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, chromeos_init_chromeos_acpi, NULL);
AIUI, `chromeos_init_chromeos_acpi()` can now be executed before `acpi_create_gnvs()`. Does it matter? I think it doesn't matter because GNVS and CNVS are separate, but I'd like to make sure it's OK.
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