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Change subject: soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPC
......................................................................
Patch Set 1: Code-Review+2
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Hello Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63635
to look at the new patch set (#2).
Change subject: mb/google/brya: Add TPM I2C for moli
......................................................................
mb/google/brya: Add TPM I2C for moli
Add TPM I2C for crota to avoid TPM I2C fail.
BUG=b:229200525
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/63635/2
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Raihow Shi has uploaded a new patch set (#4) to the change originally created by Terry Chen. ( https://review.coreboot.org/c/coreboot/+/63617 )
Change subject: mb/google/brya: Add TPM I2C for crota
......................................................................
mb/google/brya: Add TPM I2C for crota
Add TPM I2C for crota to avoid TPM I2C fail.
BUG=b:226315394
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com>
Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102
---
M src/mainboard/google/brya/Kconfig
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63617/4
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Change subject: libpayload/defconfig: enable vboot Lib Build
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63240/comment/3b424b28_aa8b9fe1
PS3, Line 9: #3461454
> Sorry, I don't quite understand the use case here and I disagree with the conclusion. […]
We require to build Coreboot (with Depthcharge) outside the ChromeOS SDK, with default configs in coreboot, we hit a compilation error after this new change. Within the ChromeOS sdk, this is managed by a separate config.<BOARD>. We wanted to avoid creation of multiple configs for each board.
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Change subject: soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPC
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Patch Set 1: Code-Review+2
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63628 )
Change subject: lib: Treat dimm addr_map 0 as not exist
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63628/comment/4851bded_1adb39ac
PS3, Line 7: not exist
nit: Maybe "invalid" is better word? Or "non-existent".
https://review.coreboot.org/c/coreboot/+/63628/comment/72967ddc_b1c325d9
PS3, Line 9: not exist
Same as above.
https://review.coreboot.org/c/coreboot/+/63628/comment/4e1a179e_3567c588
PS3, Line 10: there no HW exist
no HW exists
or
HW is unabailable / Hw is not present
File src/lib/spd_cache.c:
https://review.coreboot.org/c/coreboot/+/63628/comment/5c4c8d4e_0a916fb7
PS2, Line 159: is not exist
"does not exist"
File tests/lib/spd_cache-test.c:
https://review.coreboot.org/c/coreboot/+/63628/comment/bf8575e7_298c75c1
PS3, Line 143:
Can you add test case with .addr_map containing zero? New fragment of code should be covered by tests.
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