coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: apple/macbook21: configure the clockgen and add C3 CPU state
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Ferass EL HAFIDI, Arthur Heymans, Evgeny Zinoviev. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 ) Change subject: apple/macbook21: configure the clockgen and add C3 CPU state ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Patchset: PS4: i'd probably split the patch into the clock generator config and adding the c3 state as separate second patch, but i don't see much of a problem with having both in one patch either, since the scope is still small enough. File src/mainboard/apple/macbook21/cstates.c: https://review.coreboot.org/c/coreboot/+/63587/comment/95b76b2b_857a6f2a PS4, Line 34: .latency = 17, is this the latency value from the vendor firmware's ACPI? -- To view, visit https://review.coreboot.org/c/coreboot/+/63587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Gerrit-Change-Number: 63587 Gerrit-PatchSet: 4 Gerrit-Owner: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:34:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nipperkin: Disable PSPP for WLAN
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63593 ) Change subject: mb/google/nipperkin: Disable PSPP for WLAN ...................................................................... mb/google/nipperkin: Disable PSPP for WLAN Disable PSPP parameters for WLAN card on Nipperkin. This feature is causing S0ix resume hangs. BUG=b:227296841,b:228830362 BRANCH=guybrush TEST=Suspend stress test passes on Nipperkin Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63593 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/nipperkin/variant.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/nipperkin/variant.c b/src/mainboard/google/guybrush/variants/nipperkin/variant.c index 204ec61..9ffb2d5 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/variant.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/variant.c @@ -4,6 +4,7 @@ #include <boardid.h> #include <device/device.h> #include <soc/gpio.h> +#include <string.h> void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) { @@ -12,6 +13,9 @@ if (board_version >= 3) { dxio_descriptors[WLAN].link_aspm_L1_1 = true; dxio_descriptors[WLAN].link_aspm_L1_2 = true; + /* Disable PSPP to avoid S0ix hangs - b/228830362 */ + memset(dxio_descriptors[WLAN].port_params, 0, + sizeof(dxio_descriptors[WLAN].port_params)); } else { dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false; -- To view, visit https://review.coreboot.org/c/coreboot/+/63593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f05b92ace4aba61163194a6a638915882b8871 Gerrit-Change-Number: 63593 Gerrit-PatchSet: 4 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: cezanne: Update CPPC value
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63632 ) Change subject: cezanne: Update CPPC value ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: you'll need to rebase this one; there was a problem with an updated checkpatch version that has already been fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/63632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091ab3bbc5f94961f8b366a3fa00f50f5c9fa182 Gerrit-Change-Number: 63632 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:28:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add PMC Crashlog PCI driver
by Jonathan Zhang (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Furquan Shaikh, Francois Toguo Fotso, Subrata Banik, Daocheng Bu, Tim Wawrzynczak, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57684 ) Change subject: soc/intel/common: Add PMC Crashlog PCI driver ...................................................................... Patch Set 9: (3 comments) Patchset: PS9: Thanks for the work! We are working on this feature as well, albeit for Xeon-SP processors. File src/soc/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/57684/comment/460fc2cd_5a17fdec PS9, Line 40: crashlog record on every boot. Do you mean "enables the PMC crashlog driver to collect crashlog records on every reset"? If the PMC crashlog record was cleared prior to last running session, and there was no PMC crash during the last running session, there will be zero PMC crashlog records, correct? In such case, the PMC crashlog driver finds zero crashlog records, and hence BERT table is not populated with PMC crashlog record. The reason I would like to clarify this is because OS treats BERT table as an error of previous running session, and user gets alerted to investigate. We want to avoid false alarm. File src/soc/intel/common/block/crashlog/pmc_crashlog.c: https://review.coreboot.org/c/coreboot/+/57684/comment/667d284d_4e6dd214 PS9, Line 269: Once crashlog records are collected, should we clear the records? -- To view, visit https://review.coreboot.org/c/coreboot/+/57684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc27bbdf35fcd680be224ba0a0e642c94d29bca3 Gerrit-Change-Number: 57684 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h>
by Jack Rosenthal (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen. Jack Rosenthal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63113 ) Change subject: commonlib/bsd/elog: Include <stdint.h> instead of <inttypes.h> ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4 Gerrit-Change-Number: 63113 Gerrit-PatchSet: 3 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:26:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: apple/macbook21: configure the clockgen and add C3 CPU state
by Ferass EL HAFIDI (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Arthur Heymans, Evgeny Zinoviev. Ferass EL HAFIDI has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 ) Change subject: apple/macbook21: configure the clockgen and add C3 CPU state ...................................................................... Patch Set 4: (1 comment) File src/mainboard/apple/macbook21/Kconfig: https://review.coreboot.org/c/coreboot/+/63587/comment/fe0bc0b6_5b4c141b PS4, Line 19: DRIVERS_I2C_CK505 > Did you check if the IMAC52 has a compatible clockgen? I'm thinking about this: since the board is similar (if not exact) it should have a compatible clockgen but I don't have an iMac5,2 so I can't test. Also on most desktops there's no C2 or C3 so that might be the case on the iMac5,2 but I can't test. :/ I probably should make the coreboot build system use those drivers only on MacBook2,1 and MacBook1,1 laptops. -- To view, visit https://review.coreboot.org/c/coreboot/+/63587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Gerrit-Change-Number: 63587 Gerrit-PatchSet: 4 Gerrit-Owner: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:25:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63627 ) Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63627/comment/485a79eb_3fbc50f6 PS7, Line 63: die("SPI Cycle pending for too long!"); > > I don't know if die()ing is the right thing here; that should only be used in the rarest of circum […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:18:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/generic: Add support for i2c device detection
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Raul Rangel, Matt DeVillier, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63211 ) Change subject: drivers/i2c/generic: Add support for i2c device detection ...................................................................... Patch Set 4: (1 comment) File src/drivers/i2c/generic/generic.c: https://review.coreboot.org/c/coreboot/+/63211/comment/668e1d63_39c66fda PS4, Line 70: struct device *const busdev = i2c_busdev(dev); : if (busdev && busdev->ops->ops_i2c_bus->detect) { : if (!busdev->ops->ops_i2c_bus->detect(busdev, : dev->path.i2c.device)) { : printk(BIOS_SPEW, "%s: %s at %s -- NOT FOUND, skipping\n", path, : config->desc ? : dev->chip_ops->name, dev_path(dev)); : return; : } : } Looking at it now, it's not much more code at the client site to use the 0-byte write, e.g.: ``` struct device *const busdev = i2c_busdev(dev); if (busdev) { struct i2c_msg seg = { .slave = dev->path.i2c.device }; if (busdev->ops->ops_i2c_bus->transfer(busdev, &seg, 1)) { printk(BIOS_SPEW, "%s: %s at %s -- NOT FOUND, skipping\n", path, config->desc ? : dev->chip_ops->name, dev_path(dev)); return; } } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a4169ed6416d544773a37d29cdcc154d3c28519 Gerrit-Change-Number: 63211 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:17:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Subrata Banik (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63627 to look at the new patch set (#8). Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration This patch performs additional SPI lock configuration as per Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified all flash security recommendations are being met. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63627/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Matt DeVillier. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63561 ) Change subject: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/63561/comment/d5633343_3d0b81ef PS1, Line 377: if (segments->len == 0) > not necessarily - you still need at least 1 segment even with a zero-byte xfer, to define the slave […] Ack https://review.coreboot.org/c/coreboot/+/63561/comment/4db75a59_3861149e PS1, Line 431: if (segments->len != 0) I think it's OK to still print the message in the 0-byte write case -- To view, visit https://review.coreboot.org/c/coreboot/+/63561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518e849f4c476c264a1464886b1853af66c0b29d Gerrit-Change-Number: 63561 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 16:11:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022