coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/cmn/gpmr: Enhance GPMR driver
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63607 ) Change subject: soc/intel/cmn/gpmr: Enhance GPMR driver ...................................................................... soc/intel/cmn/gpmr: Enhance GPMR driver This patch enhances the GPMR driver to add public APIs for other IA common code drivers and/or SoC code to utilize. Also, migrated all PCR GPMR register definitions into the common `pcr_gpmr.h` header file. TEST=Able to build and boot google/redrix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I87dca55a068366cb9a26a5218589166c1723da7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63607 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/gpmr/gpmr.c A src/soc/intel/common/block/include/intelblocks/gpmr.h A src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h 3 files changed, 49 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c index 1a3a602..d0fe499 100644 --- a/src/soc/intel/common/block/gpmr/gpmr.c +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <intelblocks/dmi.h> +#include <intelblocks/gpmr.h> #include <intelblocks/pcr.h> #include <soc/pcr_ids.h> @@ -16,17 +17,22 @@ #define DMI_PCR_GPMR_EN BIT(31) /* GPMR Register read given offset */ -static uint32_t gpmr_read32(uint16_t offset) +uint32_t gpmr_read32(uint16_t offset) { return pcr_read32(PID_DMI, offset); } /* GPMR Register write given offset and val */ -static void gpmr_write32(uint16_t offset, uint32_t val) +void gpmr_write32(uint16_t offset, uint32_t val) { return pcr_write32(PID_DMI, offset, val); } +void gpmr_or32(uint16_t offset, uint32_t ordata) +{ + return pcr_or32(PID_DMI, offset, ordata); +} + /* Check for available free gpmr */ static int get_available_gpmr(void) { diff --git a/src/soc/intel/common/block/include/intelblocks/gpmr.h b/src/soc/intel/common/block/include/intelblocks/gpmr.h new file mode 100644 index 0000000..d898f32 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/gpmr.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GPMR_H +#define SOC_INTEL_COMMON_BLOCK_GPMR_H + +#include <types.h> +#include <intelblocks/pcr_gpmr.h> + +uint32_t gpmr_read32(uint16_t offset); +void gpmr_write32(uint16_t offset, uint32_t val); +void gpmr_or32(uint16_t offset, uint32_t ordata); +enum cb_err enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id); + +#endif /* SOC_INTEL_COMMON_BLOCK_GPMR_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h new file mode 100644 index 0000000..fb138f9 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H +#define SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H + +#define GPMR_LPCLGIR1 0x2730 +#define GPMR_DMICTL 0x2234 +#define GPMR_DMICTL_SRLOCK (1 << 31) +#define GPMR_LPCGMR 0x2740 +#define GPMR_GCS 0x274c +#define GPMR_GCS_BILD (1 << 0) +#define GPMR_LPCIOD 0x2770 +#define GPMR_LPCIOE 0x2774 +#define GPMR_TCOBASE 0x2778 +#define GPMR_TCOEN (1 << 1) + +#define MAX_GPMR_REGS 3 + +#define GPMR_OFFSET(x) (0x277c + (x) * 8) +#define GPMR_LIMIT_MASK 0xffff0000 +#define GPMR_BASE_SHIFT 16 +#define GPMR_BASE_MASK 0xffff + +#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) +#define GPMR_EN BIT(31) + +#endif /* SOC_INTEL_COMMON_BLOCK_PCR_GPMR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87dca55a068366cb9a26a5218589166c1723da7f Gerrit-Change-Number: 63607 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block: rename dmi folder to gpmr as starting gpmr migration
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63170 ) Change subject: intel/common/block: rename dmi folder to gpmr as starting gpmr migration ...................................................................... intel/common/block: rename dmi folder to gpmr as starting gpmr migration As a start of GPMR(General Purpose Memory Range) driver migration, 1. rename dmi folder to gpmr folder 2. rename dmi.c to gpmr.c TEST=build Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63170 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- D src/soc/intel/common/block/dmi/Makefile.inc R src/soc/intel/common/block/gpmr/Kconfig A src/soc/intel/common/block/gpmr/Makefile.inc R src/soc/intel/common/block/gpmr/gpmr.c 4 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc deleted file mode 100644 index 7d013c9..0000000 --- a/src/soc/intel/common/block/dmi/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) - -bootblock-y += dmi.c -romstage-y += dmi.c -ramstage-y += dmi.c - -endif diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/gpmr/Kconfig similarity index 100% rename from src/soc/intel/common/block/dmi/Kconfig rename to src/soc/intel/common/block/gpmr/Kconfig diff --git a/src/soc/intel/common/block/gpmr/Makefile.inc b/src/soc/intel/common/block/gpmr/Makefile.inc new file mode 100644 index 0000000..0abf61f --- /dev/null +++ b/src/soc/intel/common/block/gpmr/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) + +bootblock-y += gpmr.c +romstage-y += gpmr.c +ramstage-y += gpmr.c + +endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/gpmr/gpmr.c similarity index 100% rename from src/soc/intel/common/block/dmi/dmi.c rename to src/soc/intel/common/block/gpmr/gpmr.c -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 21 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina: Maintain a single copy of PSP Level2 entries
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63510 ) Change subject: soc/amd/sabrina: Maintain a single copy of PSP Level2 entries ...................................................................... soc/amd/sabrina: Maintain a single copy of PSP Level2 entries If verified boot uses 2 RW FW slots, configure amdfwtool to maintain single copy of PSP Level2 entries. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I94eea693139b714c321b4be89380342ec7a21222 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63510 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Makefile.inc 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index b7b538e..fdad9b7 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -189,6 +189,9 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant +OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) + # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) @@ -212,7 +215,8 @@ $(OPT_EFS_SPI_MICRON_FLAG) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --soc-name "Sabrina" \ - --flashsize $(CONFIG_ROM_SIZE) + --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_RECOVERY_AB_SINGLE_COPY) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94eea693139b714c321b4be89380342ec7a21222 Gerrit-Change-Number: 63510 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/amdfwtool: Maintain one copy of PSP Level2 entries
by Felix Held (Code Review) 14 Apr '22

14 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63509 ) Change subject: util/amdfwtool: Maintain one copy of PSP Level2 entries ...................................................................... util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 20 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 646a744..af89cad 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -857,6 +857,10 @@ if (pspdir2_b != NULL) integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, AMD_FW_RECOVERYAB_B, soc_id); + else + integrate_psp_ab(ctx, pspdir, pspdir2, ish_b_dir, + AMD_FW_RECOVERYAB_B, soc_id); + count = pspdir->header.num_entries; } else if (pspdir2 != NULL) { assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); @@ -1202,6 +1206,7 @@ AMDFW_OPT_GEC, AMDFW_OPT_COMBO, AMDFW_OPT_RECOVERY_AB, + AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, AMDFW_OPT_MULTILEVEL, AMDFW_OPT_NVRAM, @@ -1250,6 +1255,7 @@ /* PSP Directory Table items */ {"combo-capable", no_argument, 0, AMDFW_OPT_COMBO }, {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, + {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, @@ -1532,6 +1538,7 @@ cb_config.multi_level = false; cb_config.recovery_ab = false; cb_config.need_ish = false; + cb_config.recovery_ab_single_copy = false; while (1) { int optindex = 0; @@ -1560,6 +1567,10 @@ case AMDFW_OPT_RECOVERY_AB: cb_config.recovery_ab = true; break; + case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: + cb_config.recovery_ab = true; + cb_config.recovery_ab_single_copy = true; + break; case AMDFW_OPT_MULTILEVEL: cb_config.multi_level = true; break; @@ -1864,14 +1875,18 @@ pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); - if (cb_config.recovery_ab) { - /* B is same as above directories for A */ - /* Skip creating pspdir2_b here to save flash space. Related - * biosdir2_b will be skipped automatically. */ + if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { + /* Create a copy of PSP Directory 2 in the backup slot B. + Related biosdir2_b copy will be created later. */ pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); } else { + /* + * Either the platform is using only one slot or B is same as above + * directories for A. Skip creating pspdir2_b here to save flash space. + * Related biosdir2_b will be skipped automatically. + */ pspdir2_b = NULL; /* More explicitly */ } pspdir = new_psp_dir(&ctx, cb_config.multi_level); diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index d2571e5..2238638 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -279,6 +279,7 @@ bool second_gen; bool have_mb_spl; bool recovery_ab; + bool recovery_ab_single_copy; bool need_ish; } amd_cb_config; -- To view, visit https://review.coreboot.org/c/coreboot/+/63509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Gerrit-Change-Number: 63509 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Mohan Viswanathan Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: remove i2c1 in overridetree for moli
by Paul Menzel (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Raihow Shi, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63545 ) Change subject: mb/google/brask/variants/moli: remove i2c1 in overridetree for moli ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63545/comment/8e3d530f_34385466 PS5, Line 7: for moli Remove as already part of the prefix. https://review.coreboot.org/c/coreboot/+/63545/comment/2a0bc6cd_9a951e8f PS5, Line 9: is already have already has it. https://review.coreboot.org/c/coreboot/+/63545/comment/b398237d_9897f5cc PS5, Line 9: remove Remove -- To view, visit https://review.coreboot.org/c/coreboot/+/63545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Gerrit-Change-Number: 63545 Gerrit-PatchSet: 5 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:36:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Treat dimm addr_map 0 as non-existent
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Jakub Czapiga, Ivy Jian, Eric Lai, Lean Sheng Tan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63628 ) Change subject: lib: Treat dimm addr_map 0 as non-existent ...................................................................... Patch Set 7: (1 comment) File tests/lib/spd_cache-test.c: PS7: What about adding a test case for non-existent DIMMs? -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 7 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:24:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Treat dimm addr_map 0 as non-existent
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Jakub Czapiga, Ivy Jian, Eric Lai, Lean Sheng Tan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63628 ) Change subject: lib: Treat dimm addr_map 0 as non-existent ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63628/comment/120a2a8b_1cc94f89 PS7, Line 7: Treat dimm addr_map 0 as non-existent suggestion: `Check for non-existent DIMMs in check_if_dimm_changed` -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 7 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:23:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: add the smbus addr for dimm1
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Frank Wu, John Su, YH Lin, Dtrain Hsu, Ian Feng, Nick Vaccaro, Eric Lai, Amanda Hwang, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63622 ) Change subject: mb/google/brya/var/banshee: add the smbus addr for dimm1 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hi Tim and Eric, […] Hi Frank, yeah that seems like the right thing to do, if banshee does not have those DIMMs, then it doesn't make sense to have addresses for non-existent DIMMs in the code 👍 -- To view, visit https://review.coreboot.org/c/coreboot/+/63622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I708d6c3f7976891b1178e43449168090e215d122 Gerrit-Change-Number: 63622 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:22:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63544 ) Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63544/comment/10b84e2d_ade7381a PS1, Line 9: which will turn : off the eMMC controller (a true D3cold state) during the RTD3 sequence. > Ok, I modify the commit message, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:18:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: remove i2c1 in overridetree for moli
by Tim Wawrzynczak (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63545 ) Change subject: mb/google/brask/variants/moli: remove i2c1 in overridetree for moli ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Gerrit-Change-Number: 63545 Gerrit-PatchSet: 5 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 14 Apr 2022 15:18:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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