coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: apple/macbook21: configure the clockgen and add C3 CPU state
by Ferass EL HAFIDI (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Arthur Heymans, Evgeny Zinoviev, Felix Held. Ferass EL HAFIDI has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 ) Change subject: apple/macbook21: configure the clockgen and add C3 CPU state ...................................................................... Patch Set 5: (1 comment) File src/mainboard/apple/macbook21/Kconfig: https://review.coreboot.org/c/coreboot/+/63587/comment/0b0d32f0_ff0d0708 PS4, Line 19: DRIVERS_I2C_CK505 > I'll do just that, thanks! Done! -- To view, visit https://review.coreboot.org/c/coreboot/+/63587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Gerrit-Change-Number: 63587 Gerrit-PatchSet: 5 Gerrit-Owner: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 16 Apr 2022 12:19:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: apple/macbook21: configure the clockgen and add C3 CPU state
by Ferass EL HAFIDI (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Arthur Heymans, Evgeny Zinoviev, Felix Held. Ferass EL HAFIDI has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 ) Change subject: apple/macbook21: configure the clockgen and add C3 CPU state ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: So I retested the patch with coreboot master to see if it didn't break and so far, it still works properly as it should. -- To view, visit https://review.coreboot.org/c/coreboot/+/63587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Gerrit-Change-Number: 63587 Gerrit-PatchSet: 5 Gerrit-Owner: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 16 Apr 2022 12:19:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: apple/macbook21: configure the clockgen and add C3 CPU state
by Ferass EL HAFIDI (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Arthur Heymans, Evgeny Zinoviev, Felix Held. Ferass EL HAFIDI has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 ) Change subject: apple/macbook21: configure the clockgen and add C3 CPU state ...................................................................... Patch Set 5: (1 comment) File src/mainboard/apple/macbook21/cstates.c: https://review.coreboot.org/c/coreboot/+/63587/comment/66669d05_471db712 PS4, Line 34: .latency = 17, > is this the latency value from the vendor firmware's ACPI? That latency value works perfectly fine. I don't think I pulled this from the vendor firmware's ACPI however. -- To view, visit https://review.coreboot.org/c/coreboot/+/63587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib97f95599fbdf66aa55e936bdcb9cc0cd69b3824 Gerrit-Change-Number: 63587 Gerrit-PatchSet: 5 Gerrit-Owner: Ferass EL HAFIDI <vitali64pmemail(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 16 Apr 2022 12:18:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Allow for 16 additional PSP entries to be supported.
by Paul Menzel (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Bao Zheng, Jason Nien, Al Hirani. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62911 ) Change subject: amdfwtool: Allow for 16 additional PSP entries to be supported. ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62911/comment/1fa4a5a3_2c840155 PS2, Line 9: Consolidate the MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file > I'm sorry, would you be able to expand on that? I added periods at the end of sentences I commented the dot/period I meant. Commit Message: https://review.coreboot.org/c/coreboot/+/62911/comment/73952a0c_e1120411 PS4, Line 7: . I mean this dot/period. Please remove. [1] [1]: https://cbea.ms/git-commit/ -- To view, visit https://review.coreboot.org/c/coreboot/+/62911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Gerrit-Change-Number: 62911 Gerrit-PatchSet: 4 Gerrit-Owner: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Comment-Date: Sat, 16 Apr 2022 08:12:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Al Hirani <al.hirani13(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: test/lib: Add non-existent DIMMs test case in spd_cache-test
by Eric Lai (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Jakub Czapiga. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63643 ) Change subject: test/lib: Add non-existent DIMMs test case in spd_cache-test ...................................................................... Patch Set 1: (2 comments) File tests/lib/spd_cache-test.c: https://review.coreboot.org/c/coreboot/+/63643/comment/582a06b2_b85ee52c PS1, Line 73: 0 I would like to fix this, since in ROM default value is 0xff, you you never access that. In a follow up CL. https://review.coreboot.org/c/coreboot/+/63643/comment/38a05fcd_f86cdb5b PS1, Line 84: 0 same above. -- To view, visit https://review.coreboot.org/c/coreboot/+/63643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c8aa92ee0cfd5908399f4bbd305f8f306571d40 Gerrit-Change-Number: 63643 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Sat, 16 Apr 2022 03:59:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Check for non-existent DIMMs in check_if_dimm_changed
by Eric Lai (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Jakub Czapiga, Ivy Jian, Lean Sheng Tan. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63628 ) Change subject: lib: Check for non-existent DIMMs in check_if_dimm_changed ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63628/comment/6fb2c2fa_bfdcf165 PS9, Line 11: common > `commonly` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 10 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 16 Apr 2022 03:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Check for non-existent DIMMs in check_if_dimm_changed
by Eric Lai (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Jakub Czapiga, Ivy Jian, Eric Lai, Lean Sheng Tan. Hello Frank Wu, build bot (Jenkins), Jakub Czapiga, Subrata Banik, Tim Wawrzynczak, Ivy Jian, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63628 to look at the new patch set (#10). Change subject: lib: Check for non-existent DIMMs in check_if_dimm_changed ...................................................................... lib: Check for non-existent DIMMs in check_if_dimm_changed Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set it if Hw is not present. Also change the test case default to avoid 0. SODIMM SMbus address 0x50 to 0x53 is commonly used. BUG=b:213964936 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The MRC training does not be performed again after rebooting. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac --- M src/lib/spd_cache.c M tests/lib/spd_cache-test.c 2 files changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/63628/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac Gerrit-Change-Number: 63628 Gerrit-PatchSet: 10 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add PMC Crashlog PCI driver
by Jonathan Zhang (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Furquan Shaikh, Francois Toguo Fotso, Subrata Banik, Daocheng Bu, Tim Wawrzynczak, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57684 ) Change subject: soc/intel/common: Add PMC Crashlog PCI driver ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/57684/comment/ae308e3a_e7916deb PS9, Line 40: crashlog record on every boot. > You can configure the PMC so that it will collect a trace of its activity during boot; so if you ena […] Ack File src/soc/intel/common/block/crashlog/pmc_crashlog.c: https://review.coreboot.org/c/coreboot/+/57684/comment/645a353b_7d0f9118 PS9, Line 269: > Yep, that's part of the `enable` flow, see line 292 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/57684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc27bbdf35fcd680be224ba0a0e642c94d29bca3 Gerrit-Change-Number: 57684 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 16 Apr 2022 01:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/depthcharge: enable LP_CHROMEOS in depthcharge
by Julius Werner (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Martin L Roth, Jakub Czapiga, Selma Bensaid, Stefan Reinauer, Tim Wawrzynczak, Balaji Manigandan. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: payloads/depthcharge: enable LP_CHROMEOS in depthcharge ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 7 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Sat, 16 Apr 2022 00:43:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 16 Apr '22

16 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... Patch Set 18: (1 comment) Patchset: PS9: > Can we start out with mmio_base and size? Those seem very generic. Is MTK deriving the mmio_size from the ctrl_base? QC can derive the atu_base in their QC specific case separately. It's more like the ’ctrl_base‘ for MTK's SoCs, since it's the base address of the PCIe controller, and we have the MMIO space start from 0x2000_0000 [1] for accessing the BAR of PCIe devices. [1] https://review.coreboot.org/c/coreboot/+/62360/28/src/mainboard/google/cher… -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 16 Apr 2022 00:26:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022