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Change in coreboot[master]: cpu/x86/Kconfig: Guard with ARCH_X86
by Paul Menzel (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63673 ) Change subject: cpu/x86/Kconfig: Guard with ARCH_X86 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Gerrit-Change-Number: 63673 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 17 Apr 2022 11:44:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Angel Pons (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Paul Menzel, Michał Kopeć, Michael Niewöhner, Piotr Król, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63672 ) Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63672/comment/3903dcee_0472bada PS1, Line 14: Additionally, decouple temperature offset/min/max configuration from TMPIN : mode configuration, since in these SIOs, TMPINs do not have to map directly : to temperature reading registers (e.g. TMPIN1 can read to temperature reading : register 3). > Can you put that into a separate commit? +1, this can and should be done in two commits: 1. Decouple temperature offset stuff from TMPIN 2. Add support for Super I/Os with 6 temp reading regs https://review.coreboot.org/c/coreboot/+/63672/comment/7a04be3a_acf4fb68 PS1, Line 19: Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs. > Is there no way to determin the number of registers at run-time? I don't think so. But even if there was some way to detect this at runtime, it wouldn't be useful: the Super I/O on a given mainboard is most often known at build-time [1], so runtime detection code would be pointless. [1] An exception would be HP 280 G2 (see CB:48386 for details), which can have an ITE IT8625E or an ITE IT8656E depending on the BOM (Bill Of Materials) configuration. I can think of two ways to identify which Super I/O chip is on the board: either checking the chip ID bytes (global config registers 0x20 and 0x21, what util/superiotool uses to identify chips) or by reading a PCH GPIO that indicates the BOM configuration (see bootblock.c function `bootblock_mainboard_init()`, the line initialising the `brd_str` variable). Both of these methods depend on some mainboard-specific information; at the very least, that the board can only have an IT8625E or an IT8656E. I haven't implemented Super I/O support on the 280 G2 yet, and I only have the board version with IT8656E. TL;DR: Most likely not, and it wouldn't be worth it in most cases. File src/superio/ite/common/env_ctrl.c: https://review.coreboot.org/c/coreboot/+/63672/comment/df8f01a7_d86e2902 PS1, Line 138: nit: drop blank line https://review.coreboot.org/c/coreboot/+/63672/comment/84b9515b_7cebc22b PS1, Line 145: temp - 1 Looks like you could refactor this to avoid the `- 1` everywhere. -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 17 Apr 2022 09:24:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Paul Menzel (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Michał Kopeć, Michael Niewöhner, Piotr Król, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63672 ) Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63672/comment/74ff60ab_a5cb07ff PS1, Line 14: Additionally, decouple temperature offset/min/max configuration from TMPIN : mode configuration, since in these SIOs, TMPINs do not have to map directly : to temperature reading registers (e.g. TMPIN1 can read to temperature reading : register 3). Can you put that into a separate commit? https://review.coreboot.org/c/coreboot/+/63672/comment/6a70d3e1_c82771e1 PS1, Line 19: Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs. Is there no way to determin the number of registers at run-time? File src/superio/ite/common/env_ctrl.c: https://review.coreboot.org/c/coreboot/+/63672/comment/ee77d6d9_83b5bfd6 PS1, Line 125: int bool? https://review.coreboot.org/c/coreboot/+/63672/comment/e45e625f_206a6d27 PS1, Line 127: if (source >= THERMAL_SOURCE_PECI1 && source <= THERMAL_SOURCE_PECI5) : return 1; : : return 0; Something like: return (source >= THERMAL_SOURCE_PECI1 && source <= THERMAL_SOURCE_PECI5) -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 17 Apr 2022 08:47:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Angel Pons (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Michał Kopeć, Paul Menzel, Michael Niewöhner, Piotr Król, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63672 ) Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... Patch Set 1: (1 comment) Commit Message: PS1: Please wrap lines at 72 characters. For the commit summary, try to abbreviate it a bit. -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 17 Apr 2022 08:41:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/Kconfig: Guard with ARCH_X86
by Arthur Heymans (Code Review) 17 Apr '22

17 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63673 ) Change subject: cpu/x86/Kconfig: Guard with ARCH_X86 ...................................................................... cpu/x86/Kconfig: Guard with ARCH_X86 None of these options make sense on different ARCH. Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/63673/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index d5c688d..658d2aa 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,3 +1,5 @@ +if ARCH_X86 + config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT @@ -194,3 +196,5 @@ Enables the new method of locating struct cpu_info. This new method uses the %gs segment to locate the cpu_info pointer. The old method relied on the stack being CONFIG_STACK_SIZE aligned. + +endif # ARCH_X86 -- To view, visit https://review.coreboot.org/c/coreboot/+/63673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Gerrit-Change-Number: 63673 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Michał Kopeć (Code Review) 17 Apr '22

17 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63672 ) Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... superio/ite/common: Add support for SuperIOs with 6 temperature reading registers Some ITE SuperIOs such as IT8613E or IT8625E have 6 temperature reading registers, to which values can be read from any TMPINs or external sources. These SuperIOs have Temperature Source Select registers in bank 2 of EC space. Enable thermal monitoring on these SIOs by programming these registers. Additionally, decouple temperature offset/min/max configuration from TMPIN mode configuration, since in these SIOs, TMPINs do not have to map directly to temperature reading registers (e.g. TMPIN1 can read to temperature reading register 3). Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs. Based on IT8613E "Preliminary Specification V0.3 (For E Version)" and IT8625E "Preliminary Specification V0.3 (For D Version)" Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/it8613e/Kconfig 10 files changed, 126 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63672/1 diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index a713f34..f8d426d1 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -54,9 +54,9 @@ register "TMPIN1.mode" = "THERMAL_DIODE" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_PECI" - register "TMPIN3.offset" = "100" - register "TMPIN3.min" = "0" - register "TMPIN3.max" = "100" + register "TEMP3.offset" = "100" + register "TEMP3.min" = "0" + register "TEMP3.max" = "100" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan register "FAN1.smart.tmpin" = "3" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..d9eb149 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -53,7 +53,7 @@ device pci 1f.0 on # ISA bridge chip superio/ite/it8720f # Super I/O register "TMPIN1.mode" = "THERMAL_DIODE" - register "TMPIN1.offset" = "0" + register "TEMP1.offset" = "0" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..6880b85 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -102,7 +102,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN_ALL" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d7ddf9e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -72,7 +72,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33..d4bbbac 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -194,10 +194,10 @@ end chip superio/ite/it8786e register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "100" - register "TMPIN1.min" = "128" + register "TEMP1.offset" = "100" + register "TEMP1.min" = "128" register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN2.min" = "128" + register "TEMP2.min" = "128" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" register "ec.vin_mask" = "VIN_ALL" # FAN1 is CPU fan (on board) diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 36c1496..f1b7c74 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -48,4 +48,10 @@ Temperature can be read to any TMPIN from an external sensor via SST/PECI (instead of TMPIN3 only). +config SUPERIO_ITE_ENV_CTRL_6_TEMPS + bool + help + Temperature can be read to 6 temperature reading registers from external + or physical inputs, selectable using TSS registers in Bank 2. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9149c58..854e39b 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -58,7 +58,7 @@ * into TMPINx register */ static void enable_tmpin(const u16 base, const u8 tmpin, - const struct ite_ec_thermal_config *const conf) + const struct ite_ec_tmpin_config *const conf) { u8 reg; u8 reg_extra; @@ -110,18 +110,59 @@ pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); - /* Set temperature offsets */ - if (conf->mode != THERMAL_RESISTOR) { - reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); - reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; - pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); - pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); +} + +static void ite_ec_select_bank(const u16 base, const u8 bank) +{ + uint8_t reg; + + reg = pnp_read_hwm5_index(base, ITE_EC_REG_SMI_MASK_3); + reg &= ~ITE_EC_BANK_SEL_MASK; + reg |= (bank << 5); + pnp_write_hwm5_index(base, ITE_EC_REG_SMI_MASK_3, reg); +} + +static int source_is_peci(enum ite_ec_thermal_source source) +{ + if (source >= THERMAL_SOURCE_PECI1 && source <= THERMAL_SOURCE_PECI5) + return 1; + + return 0; +} + +/* + * Configure temperature reading registers (offsets, limits, sources) + */ +static void enable_temp(const u16 base, const u8 temp, + const struct ite_ec_thermal_config *const conf) + +{ + u8 reg; + + if (CONFIG(SUPERIO_ITE_ENV_CTRL_6_TEMPS)) { + /* Set temperature sources */ + ite_ec_select_bank(base, 0x2); + reg = pnp_read_hwm5_index(base, ITE_EC_REG_TSS1(temp - 1)); + reg &= ~ITE_EC_REG_TSS1_MASK(temp - 1); + reg |= conf->source << ITE_EC_REG_TSS1_OFFSET(temp - 1); + pnp_write_hwm5_index(base, ITE_EC_REG_TSS1(temp - 1), reg); + ite_ec_select_bank(base, 0x0); + + /* Enable PECI if needed */ + if (source_is_peci(conf->source)) + enable_peci(base); } + /* Set temperature offsets */ + reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); + reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[temp - 1], conf->offset); + /* Set temperature limits */ u8 max = conf->max; - pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127); - pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT[temp - 1], max ? max : 127); + pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT[temp - 1], conf->min); /* Enable the startup of monitoring operation */ reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION); @@ -286,6 +327,10 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Configure temperature reading registers */ + for (i = 0; i < ITE_EC_TEMP_CNT; ++i) + enable_temp(base, i + 1, &conf->temp[i]); + /* Enable External Sensor SMBus Host if configured */ if (conf->smbus_en) { pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, @@ -315,7 +360,13 @@ * busy state. Therefore, check the status and terminate * processes if needed. */ - for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) - if (conf->tmpin[i].mode == THERMAL_PECI) - extemp_force_idle_status(base); + if (CONFIG(SUPERIO_ITE_ENV_CTRL_6_TEMPS)) { + for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) + if (conf->tmpin[i].mode == THERMAL_PECI) + extemp_force_idle_status(base); + } else { + for (i = 0; i < ITE_EC_TEMP_CNT; ++i) + if (source_is_peci(conf->temp[i].source)) + extemp_force_idle_status(base); + } } diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 5a31e7c..21e6cea 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -119,8 +119,9 @@ : (_p / 16); \ }) -#define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) -#define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) + +static const uint8_t ITE_EC_HIGH_TEMP_LIMIT[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 }; +static const uint8_t ITE_EC_LOW_TEMP_LIMIT[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 }; #define ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE 0x50 #define ITE_EC_ADC_TEMP_CHANNEL_ENABLE 0x51 @@ -131,8 +132,14 @@ #define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55 #define ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT (1 << 7) -/* Matches length of ITE_EC_TMPIN_CNT */ -static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 }; +#define ITE_EC_REG_SMI_MASK_3 0x06 +#define ITE_EC_BANK_SEL_MASK 0x60 + +static const uint8_t ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 }; + +#define ITE_EC_REG_TSS1(x) (0x1D + ((x) / 2)) +#define ITE_EC_REG_TSS1_OFFSET(x) (((x) % 2) ? 4 : 0) +#define ITE_EC_REG_TSS1_MASK(x) (0xF << ITE_EC_REG_TSS1_OFFSET(x)) #define ITE_EC_BEEP_ENABLE 0x5C #define ITE_EC_TEMP_ADJUST_WRITE_ENABLE (1 << 7) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 2bb0780..54d9257 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -5,6 +5,12 @@ #define ITE_EC_TMPIN_CNT 3 +#if CONFIG(SUPERIO_ITE_ENV_CTRL_6_TEMPS) +#define ITE_EC_TEMP_CNT 6 +#else +#define ITE_EC_TEMP_CNT 3 +#endif + #if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CNT 5 #else @@ -12,15 +18,30 @@ #endif /* Supported thermal mode on TMPINx */ -enum ite_ec_thermal_mode { +enum ite_ec_tmpin_mode { THERMAL_MODE_DISABLED = 0, THERMAL_DIODE, THERMAL_RESISTOR, THERMAL_PECI, }; +struct ite_ec_tmpin_config { + enum ite_ec_tmpin_mode mode; +}; + +enum ite_ec_thermal_source { + THERMAL_SOURCE_TMPIN1 = 0, + THERMAL_SOURCE_TMPIN2 = 1, + THERMAL_SOURCE_TMPIN3 = 2, + THERMAL_SOURCE_PECI1 = 4, + THERMAL_SOURCE_PECI2 = 5, + THERMAL_SOURCE_PECI3 = 6, + THERMAL_SOURCE_PECI4 = 7, + THERMAL_SOURCE_PECI5 = 8, +}; + struct ite_ec_thermal_config { - enum ite_ec_thermal_mode mode; + enum ite_ec_thermal_source source; /* Offset is used for diode sensors and PECI */ u8 offset; /* Limits */ @@ -78,7 +99,12 @@ /* * Enable temperature sensors in given mode. */ - struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT]; + struct ite_ec_tmpin_config tmpin[ITE_EC_TMPIN_CNT]; + + /* + * Configure temperature reading registers. + */ + struct ite_ec_thermal_config temp[ITE_EC_TEMP_CNT]; /* * Enable a FAN in given mode. @@ -105,6 +131,13 @@ #define TMPIN2 ec.tmpin[1] #define TMPIN3 ec.tmpin[2] +#define TEMP1 ec.temp[0] +#define TEMP2 ec.temp[1] +#define TEMP3 ec.temp[2] +#define TEMP4 ec.temp[3] +#define TEMP5 ec.temp[4] +#define TEMP6 ec.temp[5] + #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2] diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index e6f01c4..9d5eb6a 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -8,4 +8,4 @@ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF - select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_6_TEMPS -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: docs/coding_style: Clarify use of GCC extensions
by Paul Menzel (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Arthur Heymans, Hung-Te Lin, Nico Huber, Julius Werner, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63660 ) Change subject: docs/coding_style: Clarify use of GCC extensions ...................................................................... Patch Set 2: (1 comment) File Documentation/contributing/coding_style.md: https://review.coreboot.org/c/coreboot/+/63660/comment/31e29aa8_3fc31268 PS2, Line 994: "Extensions to the C Language Family" section of the GCC manual Make it a link? -- To view, visit https://review.coreboot.org/c/coreboot/+/63660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11 Gerrit-Change-Number: 63660 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 17 Apr 2022 06:24:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/smbios.h: Add PCIe Gen5 slot type definitions
by Paul Menzel (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Michał Żygowski, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63653 ) Change subject: include/smbios.h: Add PCIe Gen5 slot type definitions ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e07feb23bdd6ac9f145a649b77a88db1c08624 Gerrit-Change-Number: 63653 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 17 Apr 2022 06:21:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add support for catching null deferences through debug regs
by Paul Menzel (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Robert Zieba, Nico Huber, Raul Rangel, Arthur Heymans, Tim Wawrzynczak, Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63657 ) Change subject: arch/x86: Add support for catching null deferences through debug regs ...................................................................... Patch Set 5: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63657/comment/1a9ff66a_a32a0fbb PS5, Line 9: deferences Ditto. https://review.coreboot.org/c/coreboot/+/63657/comment/f1279538_3b348758 PS5, Line 12: have been Present tense: are https://review.coreboot.org/c/coreboot/+/63657/comment/78d75780_4894080f PS5, Line 18: expected How can this be tested exactly? Does it also work in QEMU? Patchset: PS5: Can you please make sure, it also builds with clang? File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/63657/comment/0771932f_73e378ae PS5, Line 327: Enables Imperative mood seems to be used in this file: Enable. https://review.coreboot.org/c/coreboot/+/63657/comment/1aa3b797_4562727a PS5, Line 335: deferences Ditto. https://review.coreboot.org/c/coreboot/+/63657/comment/f6a203f1_a1fe768a PS5, Line 335: Enables Ditto. https://review.coreboot.org/c/coreboot/+/63657/comment/ebe77f20_26cf1837 PS5, Line 342: deferences Ditto. File src/arch/x86/breakpoint.c: https://review.coreboot.org/c/coreboot/+/63657/comment/22373d96_d2a47c13 PS5, Line 280: #if ENV_X86_64 Is it possible to check this in C code? -- To view, visit https://review.coreboot.org/c/coreboot/+/63657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I113590689046a13c2a552741bbfe7668a834354a Gerrit-Change-Number: 63657 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 17 Apr 2022 05:43:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Paul Menzel (Code Review) 17 Apr '22

17 Apr '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Angel Pons. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/ea7d9732_4c8cd716 PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms > Always enabling MCHBAR in bootblock seems reasonable to me. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 17 Apr 2022 05:32:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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