coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable SATA ports
by Andrey Petrov (Code Review) 09 Jun '23

09 Jun '23

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39918 ) Change subject: soc/intel/xeon_sp/cpx: Enable SATA ports ...................................................................... soc/intel/xeon_sp/cpx: Enable SATA ports Looks like FSP does not explicity configure SATA ports as enabled. As result some payloads (SeaBIOS, TianoCore) can detect the drives but Linux kernel does not. Turns out the kernel does not touch disabled ports, while SeaBIOS just checks all available ports. Interestingly, SKX FSP seems to be enabling all the ports. This change hooks up some common SATA code which enables all ports. TEST=booted on Cedar Island CRB, make sure 7-pin SATA drive works Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686 --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39918/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 70703d0..2f637b1 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -17,6 +17,8 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE select FSP_USES_CB_STACK + select SOC_INTEL_COMMON_BLOCK_SATA + select SOC_AHCI_PORT_IMPLEMENTED_INVERT config FSP_HEADER_PATH string "Location of FSP headers" -- To view, visit https://review.coreboot.org/c/coreboot/+/39918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686 Gerrit-Change-Number: 39918 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48658 ) Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ...................................................................... soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM. Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address. Reserved 8 KiB as that seems to be the minimal common reserved size for the TPM MMIO area. Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/alderlake/espi.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 9 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/1 diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c909030..f3c445a 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -27,6 +27,8 @@ */ static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index ad9211b9..91b4b6e 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -9,7 +9,8 @@ #include "chip.h" static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = { - { 0xfed40000, 0x8000 }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0xfedc0000, 0x4000 }, { 0xfed20800, 16 }, { 0xfed20880, 8 }, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117..b72c298 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -25,6 +25,8 @@ */ static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fcc..1ecd929 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -23,6 +23,8 @@ */ static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2f..e4977be 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857..3370999 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c6639..7c80cbf 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -21,6 +21,8 @@ static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b12..d4ea81a 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -30,6 +30,8 @@ */ static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..370a020 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -10,6 +10,8 @@ #include <chip.h> static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Gerrit-Change-Number: 48658 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382
by Arthur Heymans (Code Review) 09 Jun '23

09 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33789 Change subject: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 ...................................................................... [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 This adds a hook to the pc87382 code to specify the ACPI _HID in the case that a wacom device is hooked up to it. TODO: - the wacom code needs to know quite a lot about the SIO and has weird Kconfig hooks to force stuff that is bound to no work. - Add a function to detect the sio and disable it, if not found. Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c 6 files changed, 66 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33789/1 diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index dfbd840..45395d3 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pnp.h> #include <string.h> +#include <superio/nsc/pc87382/pc87382.h> #include "lenovo.h" #include "drivers/i2c/at24rf08c/lenovo.h" @@ -84,28 +85,10 @@ return (result = 0); } -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) +const char *nsc_pc87382_sp1_acpi_hid(void) { - acpigen_write_scope(scope); - - if (drivers_lenovo_is_wacom_present()) { - acpigen_write_device("DTR"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("WACF004"); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x200, 0x200, 1, 8, 1); - acpigen_write_irq((1 << 5)); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - - acpigen_pop_len(); + if (drivers_lenovo_is_wacom_present()) + return "WACF004"; + else + return "PNP0501"; } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index bcb94b1..2e65e56 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -17,18 +17,11 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); - - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 8cd87aa..87a2f0e 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -56,17 +56,11 @@ printk(BIOS_SPEW, "SPI configured\n"); } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { u16 pmbase; dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 9febea5..acf63cb 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -113,15 +113,9 @@ } } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h index 6826f45..480a646 100644 --- a/src/superio/nsc/pc87382/pc87382.h +++ b/src/superio/nsc/pc87382/pc87382.h @@ -21,4 +21,6 @@ #define PC87382_SP1 0x03 #define PC87382_GPIO 0x07 #define PC87382_DOCK 0x19 + +const char *nsc_pc87382_sp1_acpi_hid(void); #endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023..4d270c0 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -33,12 +35,68 @@ } } +__weak const char *nsc_pc87382_sp1_acpi_hid(void) +{ + return "PNP0501"; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87382_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + acpigen_write_scope(scope); + + switch (dev->path.pnp.device) { + case PC87382_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IOBASE not set.\n", + PC87382_SP1); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IRQ not set.\n", + PC87382_SP1); + break; + } + + acpigen_write_device("DIR"); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid(nsc_pc87382_sp1_acpi_hid()); + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header( ); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + acpigen_write_STA(0xf); + + break; + } + acpigen_pop_len(); +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87382_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Gerrit-Change-Number: 33789 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors
by Abdullah Zafar (Code Review) 09 Jun '23

09 Jun '23

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31975 Change subject: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors ...................................................................... src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors Fix trailing whitespace and space required after that ','. Signed-off-by: Abdullah Zafar <azafar.bee16seecs(a)seecs.edu.pk> Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 --- M src/drivers/aspeed/common/ast_tables.h 1 file changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31975/1 diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..f59e5a7 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -112,71 +112,71 @@ /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; @@ -187,11 +187,11 @@ { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ - (SyncNN | Charx8Dot) , 75, 3, 0x2E }, + (SyncNN | Charx8Dot), 75, 3, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ - (SyncNN | Charx8Dot) , 85, 4, 0x2E }, + (SyncNN | Charx8Dot), 85, 4, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ - (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, + (SyncNN | Charx8Dot), 0xFF, 4, 0x2E }, }; static struct ast_vbios_enhtable res_800x600[] = { @@ -243,18 +243,18 @@ /* 16:9 */ static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, }; static struct ast_vbios_enhtable res_1600x900[] = { {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; @@ -270,9 +270,9 @@ static struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x35 }, }; @@ -280,18 +280,18 @@ static struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; static struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 Gerrit-Change-Number: 31975 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code
by Arthur Heymans (Code Review) 09 Jun '23

09 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33788 Change subject: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code ...................................................................... [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code This is not wacom specific code. Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/lenovo.h M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87392/superio.c 6 files changed, 66 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33788/1 diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..c7e1b8f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,2 @@ int drivers_lenovo_is_wacom_present(void); -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15..dfbd840 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -37,8 +37,7 @@ "2263", "2266", }; -int -drivers_lenovo_is_wacom_present(void) +int drivers_lenovo_is_wacom_present(void) { const char *pn; int i; @@ -85,9 +84,7 @@ return (result = 0); } -void -drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) { acpigen_write_scope(scope); @@ -110,27 +107,5 @@ acpigen_pop_len(); } - if (have_dock_serial) { - acpigen_write_device("COMA"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0501"); - acpigen_write_name("_UID"); - /* Byte */ - acpigen_write_byte(0x2); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); - acpigen_write_irq(1 << 4); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - acpigen_pop_len(); } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 1510ab7..bcb94b1 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -19,7 +19,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 70b393cc..8cd87aa 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -58,7 +58,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 964e9c0..9febea5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -115,7 +115,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..bf4ee54 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -25,12 +27,70 @@ return; } +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87392_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case PC87392_SP2: + case PC87392_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IOBASE not set.\n", + dev->path.pnp.device); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IRQ not set.\n", + dev->path.pnp.device); + break; + } + acpigen_write_scope(scope); + const char *dev_name = dev->path.pnp.device == PC87392_SP1 + ? "COMA" : "COMB"; + acpigen_write_device(dev_name); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); + /* Byte */ + acpigen_write_byte(0x2); + + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + + /* TODO, This likely depends on dock status */ + acpigen_write_STA(0xf); + + acpigen_pop_len(); /* pop scope */ + } +} +#endif + + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87392_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Gerrit-Change-Number: 33788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: superio/ite/it8728f: hook up power_on_after_fail
by James (Code Review) 09 Jun '23

09 Jun '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34884 ) Change subject: superio/ite/it8728f: hook up power_on_after_fail ...................................................................... superio/ite/it8728f: hook up power_on_after_fail Set the Super IO registers to power the system on if power_on_after_fail is set. Change-Id: Ia06dbbbed32ba13c2d91efa6377986db8452b3f4 Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/superio/ite/it8728f/it8728f.h M src/superio/ite/it8728f/superio.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/34884/1 diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 19a04de..36fd94e 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -28,6 +28,10 @@ #define IT8728F_GPIO 0x07 /* GPIO */ #define IT8728F_IR 0x0a /* Consumer IR */ +/* Registers in LDNs */ +#define IT8728F_EC_PCR1 0xf2 +#define IT8728F_EC_PCR2 0xf4 + /* Global configuration registers. */ #define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 7107bb4..d05be54 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -20,10 +20,42 @@ #include <pc80/keyboard.h> #include <stdlib.h> #include <superio/ite/common/env_ctrl.h> +#include <option.h> #include "chip.h" #include "it8728f.h" +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +static void power_control_init(struct device *dev) +{ + int power_on = MAINBOARD_POWER_OFF; + u8 value; + + get_option(&power_on, "power_on_after_fail"); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + value = pnp_read_config(dev, IT8728F_EC_PCR1); + if (power_on == MAINBOARD_POWER_KEEP) + value |= (1 << 5); + else + value &= ~(1 << 5); + pnp_write_config(dev, IT8728F_EC_PCR1, value); + + value = pnp_read_config(dev, IT8728F_EC_PCR2); + if (power_on == MAINBOARD_POWER_ON) + value |= (1 << 5); + else + value &= ~(1 << 5); + pnp_write_config(dev, IT8728F_EC_PCR2, value); + + pnp_exit_conf_mode(dev); +} + static void it8728f_init(struct device *dev) { const struct superio_ite_it8728f_config *conf = dev->chip_info; @@ -39,6 +71,7 @@ if (!conf || !res) break; ite_ec_init(res->base, &conf->ec); + power_control_init(dev); break; case IT8728F_KBCK: set_kbc_ps2_mode(); -- To view, visit https://review.coreboot.org/c/coreboot/+/34884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06dbbbed32ba13c2d91efa6377986db8452b3f4 Gerrit-Change-Number: 34884 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Disable the eMMC controller for hatch
by V Sowmya (Code Review) 09 Jun '23

09 Jun '23

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615 Change subject: mb/google/hatch: Disable the eMMC controller for hatch ...................................................................... mb/google/hatch: Disable the eMMC controller for hatch eMMC controller is not used in hatch hence this patch adds the Kconfig option to disable the eMMC controller ACPI entries. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 711d2e9..15fe354 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP + select EXCLUDE_EMMC_INTERFACE if BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/30615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Gerrit-Change-Number: 30615 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP
by Aamir Bohra (Code Review) 09 Jun '23

09 Jun '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30664 Change subject: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP ...................................................................... mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP **** DO NOT MERGE **** Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30664/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..4a47d12 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + mem_cfg->RMT = 1; + memupd->FspmTestConfig.BdatEnable = 1; + mem_cfg->MrcFastBoot = 0; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + cannonlake_memcfg_init(mem_cfg, variant_memory_params(), &spd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Gerrit-Change-Number: 30664 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/ext_stage_cache: Use uintptr_t * as argument
by Arthur Heymans (Code Review) 09 Jun '23

09 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36560 ) Change subject: lib/ext_stage_cache: Use uintptr_t * as argument ...................................................................... lib/ext_stage_cache: Use uintptr_t * as argument This avoids a cast. Change-Id: I0bfebfd86d7b20942a5026e6437feac9ec5cd37b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/tseg_region.c M src/include/stage_cache.h M src/lib/ext_stage_cache.c 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36560/1 diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index a8b8bb7..519db61 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -68,11 +68,11 @@ return 0; } -void stage_cache_external_region(void **base, size_t *size) +void stage_cache_external_region(uintptr_t *base, size_t *size) { - if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) { + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); - *base = NULL; + *base = 0; *size = 0; } } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 3c7d9fa..9f70711 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -52,7 +52,7 @@ #endif /* Fill in parameters for the external stage cache, if utilized. */ -void stage_cache_external_region(void **base, size_t *size); +void stage_cache_external_region(uintptr_t *base, size_t *size); /* Metadata associated with each stage. */ struct stage_cache { diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 52c0d6f..f56a9a4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -31,12 +31,12 @@ static void stage_cache_create_empty(void) { struct imd *imd; - void *base; + uintptr_t base; size_t size; imd = imd_get(); stage_cache_external_region(&base, &size); - imd_handle_init(imd, size + (uintptr_t)base); + imd_handle_init(imd, size + base); printk(BIOS_DEBUG, "External stage cache:\n"); imd_create_tiered_empty(imd, 4096, 4096, 1024, 32); -- To view, visit https://review.coreboot.org/c/coreboot/+/36560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bfebfd86d7b20942a5026e6437feac9ec5cd37b Gerrit-Change-Number: 36560 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Improve comment for DISB
by Patrick Rudolph (Code Review) 09 Jun '23

09 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36650 ) Change subject: soc/intel/skylake: Improve comment for DISB ...................................................................... soc/intel/skylake: Improve comment for DISB Either documentation or FSP is wrong, as the behaviour of DISB is actually reversed. Document that and warn about clearing the bit. Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/pmc.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36650/1 diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ab9297f..3bc5c68 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -31,7 +31,16 @@ void pmc_set_disb(void) { - /* Set the DISB after DRAM init */ + /* + * Set the DISB after DRAM init. + * + * According to Document Number: 332691-002EN + * "Intel 100 Series and Intel C230 Series Chipset Family Platform + * Controller Hub (PCH) Vol2" this bit must be CLEARED after DRAM init. + * + * Tests showed that either documentation or FSP is wrong. Clearing this + * bit here causes full memory training on every boot. + */ u32 disb_val; #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCH_DEV_PMC; -- To view, visit https://review.coreboot.org/c/coreboot/+/36650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ca748ddb245cae632e423a417c6a25d52a15354 Gerrit-Change-Number: 36650 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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