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Change subject: mb/google/brya/var/kinox: Modify 15W SOC power control setting
......................................................................
Patch Set 5: Code-Review+1
(7 comments)
Patchset:
PS5:
The comment above psys_config I think needs updating
File src/mainboard/google/brya/variants/kinox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62627/comment/27594248_e7658d44
PS5, Line 41: 13.52
`5A`?
https://review.coreboot.org/c/coreboot/+/62627/comment/e0b2aa03_8e655d57
PS5, Line 43: 13.52
`5A`?
https://review.coreboot.org/c/coreboot/+/62627/comment/b8f8f6c5_0c7b59a9
PS5, Line 49: 13.52A
5A?
https://review.coreboot.org/c/coreboot/+/62627/comment/65db5726_fdb65ae0
PS5, Line 50: 13.52A
5A?
https://review.coreboot.org/c/coreboot/+/62627/comment/b5efd335_5732c790
PS5, Line 51: 13.52A
5A?
https://review.coreboot.org/c/coreboot/+/62627/comment/d4ac9c25_3a0c4486
PS5, Line 55: 13.52A
5A?
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
mb/google/brya/var/volmar: Disable thunderbolt
Volmar does not support Thunderbolt, therefore
disable all of the TBT devices in the devicetree.
The volmar fit image had been disabled already,
refer to chrome-internal:4459289
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/volmar/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62810/4
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Change subject: soc/mediatek: Pass dram info to cbmem
......................................................................
Patch Set 18:
(3 comments)
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/73c01d9a_04eec87c
PS16, Line 111: mem_chip channel array: 2
> Let's wait for the discussion on CB:59193.
Ack
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/61334/comment/76cdfd04_c6d2441e
PS18, Line 110: MEM_CHIP_LPDDR4
MEM_CHIP_LPDDR4X (and remove comment)
CB:59193 is merged. Please rebase.
File src/soc/mediatek/mt8186/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61334/comment/3c597a64_50742faf
PS18, Line 74: CPPFLAGS_common += -Isrc/commonlib/bsd/include/commonlib/bsd
Why do we need this? Can't we just include <commonlib/bsd/mem_chip_info.h> in memory.c?
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/variants/moli: set eMMC pin in bootblock
......................................................................
mb/google/brask/variants/moli: set eMMC pin in bootblock
1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin in bootblock
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
---
M src/mainboard/google/brya/variants/moli/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/62770/6
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Change subject: mb/google/brya/vell: Add companion device name to WWAN PCIe generic device
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/vell/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62771/comment/3b708c3a_bfd0fcc7
PS1, Line 157: device ref pcie_rp6 on
Please follow latest changes in https://review.coreboot.org/c/coreboot/+/62330/13. Thanks.
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Change subject: mb/google/brya: set GPP_D0 to GPO
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Hi Googler,
Due to schedule impact, would you please help to speed up the upstream process?
Thanks a lot.
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Change subject: mb/google/brya/var/kinox: Reconfigure GPIO settings
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62749/comment/531c4a1c_d12c8d24
PS2, Line 14:
> Were they incorrect in the original commit or have the schematics changed since then?
Hi Tim,
Thanks for review.
The schematics changed is from https://partnerissuetracker.corp.google.com/issues/214025396#comment15
The GPIO table from EE team is in https://partnerissuetracker.corp.google.com/issues/214025396#comment23
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62810/comment/754bf86f_aae159ba
PS2, Line 9: thunderbolot
> updated.
Done
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Change subject: mb/google/brya/var/volmar: Disable thunderbolt
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62810/comment/11f6f8dc_fea40fa8
PS2, Line 9: Disable thunderbolot(TBT) pcie for volmar.
> Can just say something like […]
updated.
https://review.coreboot.org/c/coreboot/+/62810/comment/cb7a8f55_4743f4d0
PS2, Line 9: thunderbolot
> `Thunderbolt`
updated.
Patchset:
PS2:
> I think dma0/1 should be disabled as well.
updated.
File src/mainboard/google/brya/variants/volmar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62810/comment/1062fdd0_e8168ca7
PS2, Line 91:
> Probably also need to disable […]
updated.
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