Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62847 )
Change subject: vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elements
......................................................................
vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elements
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
Change request here:https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
BUG=b:200113959
TEST=Verified on Meteor Lake platform, without any compilation error
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I1f33db43f7932cf6d165d0c70a0e2922dad00a09
---
M src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h
1 file changed, 13 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/62847/1
diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h
index eb9ce86..5576f41 100644
--- a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h
+++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/FspEas/FspApi.h
@@ -128,6 +128,7 @@
UINT8 Reserved1[20];
} FSPT_ARCH_UPD;
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
///
/// FSPM_ARCH_UPD Configuration.
///
@@ -141,12 +142,16 @@
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
- VOID *NvsBufferPtr;
+ /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64.
+ ///
+ UINT32 NvsBufferPtr;
///
/// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API.
///
- VOID *StackBase;
+ /// Note: This ought to be VOID*, but that won't allow calling this binary on x86_64.
+ ///
+ UINT32 StackBase;
///
/// Temporary stack size to be consumed inside
/// FspMemoryInit() API.
@@ -165,9 +170,14 @@
/// Optional event handler for the bootloader to be informed of events occurring during FSP execution.
/// This value is only valid if Revision is >= 2.
///
- FSP_EVENT_HANDLER *FspEventHandler;
+ /// Note: This ought to be FSP_EVENT_HANDLER*, but that won't allow calling this binary on x86_64.
+ ///
+ UINT32 FspEventHandler;
UINT8 Reserved1[4];
} FSPM_ARCH_UPD;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
typedef struct {
///
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62776 )
Change subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62776/comment/88a73078_6e4f1a28
PS2, Line 11: After we disable unused PCIe and SATA
: pins, the measured power consumption meets Intel reuqired low power
: consumption.
Please document the exact numbers.
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Subrata Banik has uploaded a new patch set (#43) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/59638 )
Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
FSP 2.3 spec introduced FSP_NON_VOLATILE_STORAGE_HOB2 HOB version
for NV data storage. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated
from FSP 2.3 onwards and is maintained for backward compatibility only.
This patch implements the parsing method for
FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first
searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue
to search for FSP_NON_VOLATILE_STORAGE_HOB HOB.
BUG=b:200113959
TEST=Verified on sapphire rapids and meteor lake FSP platform that
introduces FSP_NON_VOLATILE_STORAGE_HOB2 for retrieving MRC cached data.
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
2 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/43
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Hello Anil Kumar K, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62787
to look at the new patch set (#3).
Change subject: include/efi: Clean up efi_datatype.h file
......................................................................
include/efi: Clean up efi_datatype.h file
This patch cleans up `efi_datatype.h` to allow other SoC and/or driver
code to use this file.
`PiPei.h` file only gets added from UDK2017 hence, the platform with the
older EDK2 base (prior to UDK2017) is unable to resolve this file
dependency.
This CL removed the `PiPei.h` header and only added the required header
file `PiPeiCis.h` for platforms with UDK base >= 2017.
BUG=b:200113959
TEST=Able to build Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5
---
M src/include/efi/efi_datatype.h
1 file changed, 9 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62787/3
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Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62704 )
Change subject: mb/google/dedede/var/galtic: update Wifi SAR for for galnat
......................................................................
Patch Set 5: Code-Review+1
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Change subject: src/driver/wifi: Add _DSM method for DDRRFIM
......................................................................
Patch Set 19:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/61020/comment/bcc126c7_0ba63a09
PS19, Line 537: dev = dev->link_list->children;
: const struct drivers_wifi_generic_config *config = dev->chip_info;
: bool is_cnvi_ddr_rfim_enabled;
:
: is_cnvi_ddr_rfim_enabled = config->enable_cnvi_ddr_rfim;
> Please correct me here if I am wrong, I thought since the value is already stored in the structure i […]
Also I tried the new patch you have pushed https://review.coreboot.org/c/coreboot/+/62746
along with earlier suggestion but the boolean variable is still returning zero
May be we keep it this way for now ?
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Change subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
......................................................................
Patch Set 2: Code-Review+1
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 )
Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 4: Code-Review+2
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