coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/intel/denverton_ns/cpu: Get CPU frequencies for SMBIOS type 4
by Sean Rhodes (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Name of user not set #1004162, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62270 ) Change subject: soc/intel/denverton_ns/cpu: Get CPU frequencies for SMBIOS type 4 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62270/comment/91bd3dca_80677c6a PS2, Line 12: On a Harcuvar CRB, Tianocore reports a CPU running at 2.4Ghz instead of Wrap at 72 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6249b0f74b34ec5ca73351eda00604089b7c3581 Gerrit-Change-Number: 62270 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1004162 Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Name of user not set #1004162 Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 16 Mar 2022 14:05:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: device/pci_ops.h: Only allow PCI ops on DEVICE_PATH_PCI
by Arthur Heymans (Code Review) 16 Mar '22

16 Mar '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62375 ) Change subject: device/pci_ops.h: Only allow PCI ops on DEVICE_PATH_PCI ...................................................................... Abandoned NOT worth it IMO -- To view, visit https://review.coreboot.org/c/coreboot/+/62375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c4166320fbadf3ce5f4a6f291e3b9d5f8f5e43 Gerrit-Change-Number: 62375 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/amd/sabrina: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62863 to look at the new patch set (#3). Change subject: soc/amd/sabrina: Add counter initializers ...................................................................... soc/amd/sabrina: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224618411 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d --- M src/soc/amd/sabrina/fsp_m_params.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62863/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Gerrit-Change-Number: 62863 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/skyrim: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Jon Murphy. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62864 to look at the new patch set (#2). Change subject: mb/google/skyrim: Add counter initializers ...................................................................... mb/google/skyrim: Add counter initializers Some counters are not being initialized in the SOC code and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. Set the counters in the mainboard to prevent the indeterminate state. BUG=b:224618411 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I69ad46a3c717bd6dee0f5d9daa5cf65696046be9 --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62864/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69ad46a3c717bd6dee0f5d9daa5cf65696046be9 Gerrit-Change-Number: 62864 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/skyrim: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62864 ) Change subject: mb/google/skyrim: Add counter initializers ...................................................................... mb/google/skyrim: Add counter initializers Some counters are not being initialized in the SOC code and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. Set the counters in the mainboard to prevent the indeterminate state. BUG=b:224618411 TEST=builds Change-Id: I69ad46a3c717bd6dee0f5d9daa5cf65696046be9 --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62864/1 diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 56bd9f3..4fabeb9 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -8,4 +8,7 @@ const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { /* TODO: Initialize DXIO and DDI descriptors */ + /* Set counters to 0 for now to avoid indeterminate state */ + *ddi_num = 0; + *ddi_descs = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/62864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69ad46a3c717bd6dee0f5d9daa5cf65696046be9 Gerrit-Change-Number: 62864 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/denverton_ns/cpu: Get CPU frequencies for SMBIOS type 4
by Name of user not set (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Sean Rhodes, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Name of user not set #1004162 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62270 ) Change subject: soc/intel/denverton_ns/cpu: Get CPU frequencies for SMBIOS type 4 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Friendly ping 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/62270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6249b0f74b34ec5ca73351eda00604089b7c3581 Gerrit-Change-Number: 62270 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1004162 Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 16 Mar 2022 13:30:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/sabrina: Add counter initializers
by Jon Murphy (Code Review) 16 Mar '22

16 Mar '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62863 ) Change subject: soc/amd/sabrina: Add counter initializers ...................................................................... soc/amd/sabrina: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224618411 TEST=builds Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d --- M src/soc/amd/sabrina/fsp_m_params.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62863/1 diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c index f069ba8..9e833a4 100644 --- a/src/soc/amd/sabrina/fsp_m_params.c +++ b/src/soc/amd/sabrina/fsp_m_params.c @@ -49,8 +49,8 @@ { const fsp_dxio_descriptor *fsp_dxio; const fsp_ddi_descriptor *fsp_ddi; - size_t num_dxio; - size_t num_ddi; + size_t num_dxio = 0; + size_t num_ddi = 0; mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); -- To view, visit https://review.coreboot.org/c/coreboot/+/62863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Gerrit-Change-Number: 62863 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/adl: Remove IOM Mctp command from TCSS ASL
by Maulik V Vaghela (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62861 to look at the new patch set (#2). Change subject: soc/intel/adl: Remove IOM Mctp command from TCSS ASL ...................................................................... soc/intel/adl: Remove IOM Mctp command from TCSS ASL TCSS ASL code was carried forward from TGL and it used to follow the same sequence. Recently as part of s0ix hang issue, it was found that sending IOM MCTP command as part of TCSS D3 Cold enter-exit sequence created an issue. Due to change in hardware sequence, ADL should not set/reset IOM MCTP Bit during D3 cold entry or exit. This patch removes the bit setting from ASL file to prevent hang in the system BUG=b:220796339 BRANCH=firmware-brya-14505.B TEST=Check if hang issue is resolved with the CL and no other regression observed Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/acpi/tcss.asl 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/62861/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Gerrit-Change-Number: 62861 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/adl: Remove IOM Mctp command from TCSS ASL
by Maulik V Vaghela (Code Review) 16 Mar '22

16 Mar '22

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62861 ) Change subject: soc/intel/adl: Remove IOM Mctp command from TCSS ASL ...................................................................... soc/intel/adl: Remove IOM Mctp command from TCSS ASL TCSS ASL code was carried forward from TGL and it used to follow the same sequence. Recently as part of s0ix hang issue, it was found that sending IOM MCTP command as part of TCSS D3 Cold enter-exit sequence created an issue. Due to change in hardware sequence, ADL should not set/reset IOM MCTP during D3 cold entry or exit. This patch removes the bit setting from ASL file to prevent hang in the system BUG=b:220796339 BRANCH=firmware-brya-14505.B TEST=Check if hang issue is resolved with the CL and no other regression observed Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/acpi/tcss.asl 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/62861/1 diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 81c2432..73823f8 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -354,12 +354,6 @@ Offset(0x10), RBAR, 64 /* RegBar, offset 0x7110 in MCHBAR */ } - Field (MBAR, DWordAcc, NoLock, Preserve) - { - Offset(0x304), /* PRIMDN_MASK1_0_0_0_MCHBAR_IMPH, offset 0x7404 */ - , 31, - TCD3, 1 /* [31:31] TCSS IN D3 bit */ - } /* * Operation region defined to access the pCode mailbox interface. Get the MCHBAR @@ -698,11 +692,6 @@ Else { /* - * Program IOP MCTP Drop (TCSS_IN_D3) after D3 cold exit and - * acknowledgement by IOM. - */ - TCD3 = 0 - /* * If the TCSS Deven is cleared by BIOS Mailbox request, then * restore to previously saved value of TCSS DEVNE. */ @@ -749,11 +738,6 @@ } } - /* - * Program IOM MCTP Drop (TCSS_IN_D3) in D3Cold entry before entering D3 cold. - */ - TCD3 = 1 - /* Request IOM for D3 cold entry sequence. */ TD3C = 1 } -- To view, visit https://review.coreboot.org/c/coreboot/+/62861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb Gerrit-Change-Number: 62861 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/alderlake/retimer: Change loglevel prefix
by Wisley Chen (Code Review) 16 Mar '22

16 Mar '22

Attention is currently required from: Chen Wisley. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62821 ) Change subject: soc/intel/alderlake/retimer: Change loglevel prefix ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62821/comment/d03acf94_9ba65469 PS1, Line 9: It shows the ec mapped port, so change the loglevel to BIOS_INFO. > suggestion: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5 Gerrit-Change-Number: 62821 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Comment-Date: Wed, 16 Mar 2022 12:36:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022