coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62774 ) Change subject: soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC ...................................................................... soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC This patch refactors the current P2SB common code driver to accommodate the future SoC platform with provision of more than one P2SB IP in disaggregated die architecture. IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is renamed as SoC in MTL.) P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c is added only for PCH/SoC P2SB. BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/p2sb/Kconfig M src/soc/intel/common/block/p2sb/Makefile.inc 2 files changed, 16 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/p2sb/Kconfig b/src/soc/intel/common/block/p2sb/Kconfig index 7f292cd..ff20255 100644 --- a/src/soc/intel/common/block/p2sb/Kconfig +++ b/src/soc/intel/common/block/p2sb/Kconfig @@ -1,5 +1,11 @@ -config SOC_INTEL_COMMON_BLOCK_P2SB +config SOC_INTEL_COMMON_BLOCK_BASE_P2SB bool depends on SOC_INTEL_COMMON_BLOCK_PCR help - Intel Processor common P2SB driver + Intel Processor common P2SB base driver + +config SOC_INTEL_COMMON_BLOCK_P2SB + bool + select SOC_INTEL_COMMON_BLOCK_BASE_P2SB + help + Intel Processor common P2SB driver for PCH or SoC die diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index 5c6378e..dbf4545 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,8 +1,8 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB),y) -bootblock-y += p2sb.c -romstage-y += p2sb.c -ramstage-y += p2sb.c -ramstage-y += p2sblib.c -smm-y += p2sb.c -smm-y += p2sblib.c -endif +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c + +# p2sb.c for PCH and SoC die P2SB IP +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb Gerrit-Change-Number: 62774 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: set eMMC pin in bootblock
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62770 ) Change subject: mb/google/brask/variants/moli: set eMMC pin in bootblock ...................................................................... mb/google/brask/variants/moli: set eMMC pin in bootblock 1.Assert eMMC enable pin in bootblock 2.Deassert eMMC reset pin in bootblock BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62770 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/moli/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/gpio.c b/src/mainboard/google/brya/variants/moli/gpio.c index 54406ff9..6ba605e 100644 --- a/src/mainboard/google/brya/variants/moli/gpio.c +++ b/src/mainboard/google/brya/variants/moli/gpio.c @@ -69,6 +69,8 @@ static const struct pad_config early_gpio_table[] = { /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* @@ -86,6 +88,8 @@ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* F14 : GSXDIN ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_F14, 1, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19 Gerrit-Change-Number: 62770 Gerrit-PatchSet: 7 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: qualcomm/sc7280: Add mdp clock support to turbo in coreboot
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62371 ) Change subject: qualcomm/sc7280: Add mdp clock support to turbo in coreboot ...................................................................... qualcomm/sc7280: Add mdp clock support to turbo in coreboot This change supports the configuration and enablement of mdp clock to vote for turbo and supports different display panel resolutions and framerates. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371 Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/sc7280/clock.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 434eeee..746035c 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -201,6 +201,11 @@ .src = SRC_GCC_DISP_GPLL0_CLK, .div = QCOM_CLOCK_DIV(2), }, + { + .hz = 400 * MHz, + .src = SRC_GCC_DISP_GPLL0_CLK, + .div = QCOM_CLOCK_DIV(1.5), + }, }; static struct clock_rcg *mdss_clock[MDSS_CLK_COUNT] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/62371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71 Gerrit-Change-Number: 62371 Gerrit-PatchSet: 11 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-MessageType: merged

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Change in coreboot[master]: qualcomm/sc7280: Add display external clock support in coreboot
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59611 ) Change subject: qualcomm/sc7280: Add display external clock support in coreboot ...................................................................... qualcomm/sc7280: Add display external clock support in coreboot Add support for EDP (Embedded DisplayPort) clocks in coreboot. This change supports the configuration and enablement of EDP PIXEL, LINK, LINK_INTF and AUX clocks. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611 Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/clock.h 2 files changed, 53 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index ddc8d3d..434eeee 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -203,20 +203,28 @@ }, }; -static struct clock_rcg_mnd *mdss_clock[MDSS_CLK_COUNT] = { - [MDSS_CLK_PCLK0] = &mdss->pclk0, +static struct clock_rcg *mdss_clock[MDSS_CLK_COUNT] = { [MDSS_CLK_MDP] = &mdss->mdp, [MDSS_CLK_VSYNC] = &mdss->vsync, [MDSS_CLK_ESC0] = &mdss->esc0, [MDSS_CLK_BYTE0] = &mdss->byte0, [MDSS_CLK_BYTE0_INTF] = &mdss->byte0, - [MDSS_CLK_AHB] = &mdss->ahb, + [MDSS_CLK_AHB] = &mdss->mdss_ahb, + [MDSS_CLK_EDP_LINK] = &mdss->edp_link, + [MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link, + [MDSS_CLK_EDP_AUX] = &mdss->edp_aux, +}; + +static struct clock_rcg_mnd *mdss_clock_mnd[MDSS_CLK_COUNT] = { + [MDSS_CLK_PCLK0] = &mdss->pclk0, + [MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel, }; static u32 *mdss_cbcr[MDSS_CLK_COUNT] = { [GCC_DISP_AHB] = &gcc->disp_ahb_cbcr, [GCC_DISP_HF_AXI] = &gcc->disp_hf_axi_cbcr, [GCC_DISP_SF_AXI] = &gcc->disp_sf_axi_cbcr, + [GCC_EDP_CLKREF_EN] = &gcc->edp_clkref_en, [MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr, [MDSS_CLK_MDP] = &mdss->mdp_cbcr, [MDSS_CLK_VSYNC] = &mdss->vsync_cbcr, @@ -224,6 +232,10 @@ [MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr, [MDSS_CLK_ESC0] = &mdss->esc0_cbcr, [MDSS_CLK_AHB] = &mdss->ahb_cbcr, + [MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel_cbcr, + [MDSS_CLK_EDP_LINK] = &mdss->edp_link_cbcr, + [MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link_intf_cbcr, + [MDSS_CLK_EDP_AUX] = &mdss->edp_aux_cbcr, }; static u32 *gdsc[MAX_GDSC] = { @@ -401,8 +413,16 @@ mdss_clk_cfg.n = n; mdss_clk_cfg.d_2 = d_2; - return clock_configure((struct clock_rcg *)mdss_clock[clk_type], - &mdss_clk_cfg, hz, 0); + switch (clk_type) { + case MDSS_CLK_EDP_PIXEL: + case MDSS_CLK_PCLK0: + return clock_configure((struct clock_rcg *) + mdss_clock_mnd[clk_type], + &mdss_clk_cfg, hz, 0); + default: + return clock_configure(mdss_clock[clk_type], + &mdss_clk_cfg, hz, 0); + } } enum cb_err mdss_clock_enable(enum clk_mdss clk_type) diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h index a0694ba..744734e 100644 --- a/src/soc/qualcomm/sc7280/include/soc/clock.h +++ b/src/soc/qualcomm/sc7280/include/soc/clock.h @@ -89,23 +89,34 @@ u32 esc0_cbcr; u8 _res3[0x1050 - 0x103c]; u32 ahb_cbcr; - u8 _res4[0x1078 - 0x1054]; + u32 edp_pixel_cbcr; + u32 edp_link_cbcr; + u32 edp_link_intf_cbcr; + u32 edp_aux_cbcr; + u8 _res4[0x1078 - 0x1064]; struct clock_rcg_mnd pclk0; u8 _res5[0x1090 - 0x108c]; - struct clock_rcg_mnd mdp; + struct clock_rcg mdp; u8 _res6[0x10c0 - 0x1098]; - struct clock_rcg_mnd vsync; + struct clock_rcg vsync; u8 _res7[0x10d8 - 0x10c8]; - struct clock_rcg_mnd byte0; - u8 _res8[0x10f4 - 0x10ec]; - struct clock_rcg_mnd esc0; - u8 _res9[0x1170 - 0x1108]; - struct clock_rcg_mnd ahb; - u8 _res10[0x20000 - 0x1178]; + struct clock_rcg byte0; + u8 _res8[0x10f4 - 0x10e0]; + struct clock_rcg esc0; + u8 _res9[0x1170 - 0x10fc]; + struct clock_rcg mdss_ahb; + u8 _res10[0x1188 - 0x1178]; + struct clock_rcg_mnd edp_pixel; + u8 _res11[0x11a0 - 0x119c]; + struct clock_rcg edp_link; + u8 _res12[0x11d0 - 0x11a8]; + struct clock_rcg edp_aux; + u8 _res13[0x20000 - 0x11d8]; }; check_member(sc7280_disp_cc, pclk0_cbcr, 0x1010); check_member(sc7280_disp_cc, vsync_cbcr, 0x102c); check_member(sc7280_disp_cc, ahb_cbcr, 0x1050); +check_member(sc7280_disp_cc, edp_aux_cbcr, 0x1060); struct sc7280_pcie { u32 pcie_1_bcr; @@ -205,7 +216,8 @@ struct clock_rcg_mnd sdcc1; u8 _res20[0x8c004 - 0x75020]; u32 pcie_clkref_en; - u8 _res21[0x8d000 - 0x8c008]; + u32 edp_clkref_en; + u8 _res21[0x8d000 - 0x8c00c]; struct sc7280_pcie pcie_1; u8 _res22[0x90010 - 0x8e020]; u32 aggre_noc_pcie_tbu_cbcr; @@ -226,6 +238,7 @@ check_member(sc7280_gcc, usb_phy_cfg_ahb2phy_bcr, 0x6a000); check_member(sc7280_gcc, sdcc1_ahb_cbcr, 0x75004); check_member(sc7280_gcc, pcie_clkref_en, 0x8c004); +check_member(sc7280_gcc, edp_clkref_en, 0x8c008); check_member(sc7280_gcc, aggre_noc_pcie_tbu_cbcr, 0x90010); check_member(sc7280_gcc, usb30_sec_bcr, 0x9e000); @@ -293,6 +306,7 @@ GCC_DISP_AHB, GCC_DISP_HF_AXI, GCC_DISP_SF_AXI, + GCC_EDP_CLKREF_EN, MDSS_CLK_PCLK0, MDSS_CLK_MDP, MDSS_CLK_VSYNC, @@ -300,6 +314,10 @@ MDSS_CLK_BYTE0_INTF, MDSS_CLK_ESC0, MDSS_CLK_AHB, + MDSS_CLK_EDP_PIXEL, + MDSS_CLK_EDP_LINK, + MDSS_CLK_EDP_LINK_INTF, + MDSS_CLK_EDP_AUX, MDSS_CLK_COUNT }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Gerrit-Change-Number: 59611 Gerrit-PatchSet: 29 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Set gpio override to board_0
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62806 ) Change subject: mb/google/nissa/var/nivviks: Set gpio override to board_0 ...................................................................... mb/google/nissa/var/nivviks: Set gpio override to board_0 Follow the latest schematic change, gpio will match the baseboard. Return the current table as override. BUG=b:223677877 TEST=audio is functional on board_0. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/brya/variants/nivviks/gpio.c 1 file changed, 10 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c index a5f9cb8..db3b9e3 100644 --- a/src/mainboard/google/brya/variants/nivviks/gpio.c +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -2,11 +2,12 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <commonlib/helpers.h> #include <soc/gpio.h> /* Pad configuration in ramstage */ -static const struct pad_config override_gpio_table[] = { +static const struct pad_config board_id0_overrides[] = { /* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */ @@ -58,8 +59,14 @@ const struct pad_config *variant_gpio_override_table(size_t *num) { - *num = ARRAY_SIZE(override_gpio_table); - return override_gpio_table; + const uint32_t id = board_id(); + if (id == BOARD_ID_UNKNOWN || id == 0) { + *num = ARRAY_SIZE(board_id0_overrides); + return board_id0_overrides; + } + + *num = 0; + return NULL; } const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/62806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e Gerrit-Change-Number: 62806 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/chromeec/ec_smbios: Set system manufacturer for ChromeOS devices
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62796 ) Change subject: ec/chromeec/ec_smbios: Set system manufacturer for ChromeOS devices ...................................................................... ec/chromeec/ec_smbios: Set system manufacturer for ChromeOS devices Currently, many Linux drivers use DMI quirks to identify ChromeOS devices and handle them accordingly: namely they look for the SMBIOS system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be coreboot. Historically this was consistently the case, but recent model ChromeOS devices allow the OEM to set the mainboard manufacturer, which is also the default system manufacturer. This breaks many DMI quirks, notably ones used by SOF (sound open firmware) for audio. To fix this, set the system manufactuer for ChromeOS devices to "Google" for devices selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID, leaving the OEM customization in place for the mainboard manufacturer. Since boards selecting CONFIG_EC_GOOGLE_CHROMEEC_SKUID are the only ones overriding the default mainboard manufacturer, they are the only ones which need this correction. Test: build/boot google/bloog with Linux 5.16, verify SOF drivers correctly detect device as a Chromebook and load the appropriate audio firmware. Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62796 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec_smbios.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec_smbios.c b/src/ec/google/chromeec/ec_smbios.c index 1ee7283..aedcf85 100644 --- a/src/ec/google/chromeec/ec_smbios.c +++ b/src/ec/google/chromeec/ec_smbios.c @@ -37,3 +37,8 @@ return manuf; } + +const char *smbios_system_manufacturer(void) +{ + return "Google"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Gerrit-Change-Number: 62796 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Enable LTE function by FW_CONFIG option
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Aseda Aboagye, Ivan Chen, Tim Wawrzynczak, Teddy Shih, Paul Fagerburg, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62801 ) Change subject: mb/google/dedede/var/beadrix: Enable LTE function by FW_CONFIG option ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/dedede/variants/beadrix/gpio.c: https://review.coreboot.org/c/coreboot/+/62801/comment/80f288bb_45c145f2 PS1, Line 91: BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); could fw_config_handle also be called directly from the mainboard code? i'd say that calling it via BOOT_STATE_INIT_ENTRY obfuscates the code flow a bit and without having looked closely into this i don't see a strong reason to use BOOT_STATE_INIT_ENTRY here -- To view, visit https://review.coreboot.org/c/coreboot/+/62801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb Gerrit-Change-Number: 62801 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jack Cheng <jack.cheng(a)ecs.corp-partner.google.com> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 14:35:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: $(TOP)/Makefile.inc: Handle the folder common before specific one
by Bao Zheng (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Julius Werner, Zheng Bao, Elyes Haouas, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao, Elyes Haouas, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62750 to look at the new patch set (#7). Change subject: $(TOP)/Makefile.inc: Handle the folder common before specific one ...................................................................... $(TOP)/Makefile.inc: Handle the folder common before specific one Put src/soc/*/common before src/soc/*/*, just like src/superio/common is before src/superio/*, can make the variables in common Makefile get the expected value before they are used in other subdirs. The duplicated "common" in the result subdirs-y string is eliminated by "-include" directive. Then we can put some common variables in all the subdir Makefile.inc to the common Makefile.inc to reduce code redundancy. Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/62750/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Gerrit-Change-Number: 62750 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax...
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62727 ) Change subject: soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values ...................................................................... soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values Add ADL-P MCH ID 4, 8, 9, 10 into this list. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index f0e0ac2..2f3027d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -311,9 +311,13 @@ switch (mch_id) { case PCI_DID_INTEL_ADL_P_ID_1: case PCI_DID_INTEL_ADL_P_ID_3: + case PCI_DID_INTEL_ADL_P_ID_4: case PCI_DID_INTEL_ADL_P_ID_5: case PCI_DID_INTEL_ADL_P_ID_6: case PCI_DID_INTEL_ADL_P_ID_7: + case PCI_DID_INTEL_ADL_P_ID_8: + case PCI_DID_INTEL_ADL_P_ID_9: + case PCI_DID_INTEL_ADL_P_ID_10: tdp = get_cpu_tdp(); if (tdp == TDP_45W) return ICC_MAX_TDP_45W; -- To view, visit https://review.coreboot.org/c/coreboot/+/62727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e Gerrit-Change-Number: 62727 Gerrit-PatchSet: 3 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: $(TOP)/Makefile.inc: Handle the folder common before specific one
by Bao Zheng (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Julius Werner, Zheng Bao, Elyes Haouas, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62750 ) Change subject: $(TOP)/Makefile.inc: Handle the folder common before specific one ...................................................................... Patch Set 6: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/62750/comment/1b3405dc_1b1f7d5c PS6, Line 84: (filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*)) > Add a function? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Gerrit-Change-Number: 62750 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 17 Mar 2022 14:30:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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