coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen
by Karthik Ramasubramanian (Code Review) 17 Mar '22

17 Mar '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62315 ) Change subject: mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen ...................................................................... mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen For galnat platform, support 2nd ELAN touchscreen via SSFC. Define FW_CONFIG bits 39 - 40 (SSFC bits 7-8) for touchscreen controller switch. BUG=b:221002826 TEST=touch screen is functional. Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62315 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 29 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve Ivan Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 8004736..73a5f49 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -1,4 +1,12 @@ fw_config + field TOUCHSCREEN_SOURCE 39 40 + option TOUCHSCREEN_UNPROVISIONED 0 + option TOUCHSCREEN_ELAN1001 1 + option TOUCHSCREEN_ELAN9008 2 + end +end + +fw_config field AUDIO_CODEC_SOURCE 41 43 option AUDIO_CODEC_UNPROVISIONED 0 option AUDIO_CODEC_ALC5682 1 @@ -165,7 +173,27 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - device i2c 10 on end + device i2c 10 on + probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN1001 + probe TOUCHSCREEN_SOURCE TOUCHSCREEN_UNPROVISIONED + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "7" + register "generic.reset_delay_ms" = "70" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TOUCHSCREEN_SOURCE TOUCHSCREEN_ELAN9008 + end end end # I2C 2 device pci 19.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/62315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3501205b147c9dc3c96ce8381a3e7492ae8258e Gerrit-Change-Number: 62315 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Subrata Banik (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Wonkyu Kim, Tim Wawrzynczak, John Zhao, Angel Pons, Nick Vaccaro, Eric Lai, Patrick Rudolph, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/p2sb/p2sblib.c: https://review.coreboot.org/c/coreboot/+/62778/comment/b8959c09_8306c8a1 PS3, Line 13: uint32_t low_bar, uint32_t high_bar > In this topic, just wondering would pci support 64 bit read/write 😎 I thought Felix meant like this void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar) { /* Enable PCR Base addresses */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (uint32_t)bar); pci_write_config32(dev, PCI_BASE_ADDRESS_1, (uint32_t)(bar >> 32)); .... } -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 17 Mar 2022 14:58:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wifi/generic: Fix properties in generic-under-PCI device case
by Tim Wawrzynczak (Code Review) 17 Mar '22

17 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62746 ) Change subject: drivers/wifi/generic: Fix properties in generic-under-PCI device case ...................................................................... drivers/wifi/generic: Fix properties in generic-under-PCI device case In the devicetree case where a generic device underneath the Intel PCI CNVi device carries the device properties, the incorrect device was passed to wifi_ssdt_write_properties. Also while here, update the UUID for `DmaProperty` to match what Microsoft defined here: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-… BUG=b:215424986, b:220639445 TEST=dump SSDT and see that _PRW for CNVi device is no longer garbage, but contains the value from the devicetree (GPE0_PME_B0). Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62746 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/generic.c 2 files changed, 29 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, approved Varshit B Pandya: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 63faae0..ef18f6d 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -26,8 +26,8 @@ /* Unique ID for the WIFI _DSM */ #define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" -/* Unique ID for the Wifi _DSD */ -#define ACPI_DSD_UNTRUSTED_UUID "88566a92-1a61-466d-949a-6d12809d480c" +/* ID for the Wifi DmaProperty _DSD */ +#define ACPI_DSD_DMA_PROPERTY_UUID "70D24161-6DD5-4C9E-8070-705531292865" __weak int get_wifi_sar_limits(union wifi_sar_limits *sar_limits) { @@ -506,24 +506,25 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *scope) { - const struct drivers_wifi_generic_config *config = dev->chip_info; - /* Scope */ acpigen_write_scope(scope); - if (config) { - /* Wake capabilities */ - acpigen_write_PRW(config->wake, ACPI_S3); + if (dev->path.type == DEVICE_PATH_GENERIC) { + const struct drivers_wifi_generic_config *config = dev->chip_info; + if (config) { + /* Wake capabilities */ + acpigen_write_PRW(config->wake, ACPI_S3); - /* Add _DSD for DmaProperty property. */ - if (config->is_untrusted) { - struct acpi_dp *dsd, *pkg; + /* Add _DSD for DmaProperty property. */ + if (config->is_untrusted) { + struct acpi_dp *dsd, *pkg; - dsd = acpi_dp_new_table("_DSD"); - pkg = acpi_dp_new_table(ACPI_DSD_UNTRUSTED_UUID); - acpi_dp_add_integer(pkg, "DmaProperty", 1); - acpi_dp_add_package(dsd, pkg); - acpi_dp_write(dsd); + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(ACPI_DSD_DMA_PROPERTY_UUID); + acpi_dp_add_integer(pkg, "DmaProperty", 1); + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + } } } @@ -567,7 +568,9 @@ return; wifi_ssdt_write_device(dev, path); - wifi_ssdt_write_properties(dev, path); + const struct device *child = dev->link_list->children; + if (child && child->path.type == DEVICE_PATH_GENERIC) + wifi_ssdt_write_properties(child, path); } const char *wifi_pcie_acpi_name(const struct device *dev) diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 5aaedae..1187b332 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -21,6 +21,7 @@ .enable_resources = pci_dev_enable_resources, .init = wifi_pci_dev_init, .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = wifi_pcie_acpi_name, .acpi_fill_ssdt = wifi_pcie_fill_ssdt, @@ -41,6 +42,11 @@ #endif }; +struct device_operations wifi_generic_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + static bool is_cnvi(const struct device *dev) { return dev && dev->path.type != DEVICE_PATH_PCI; @@ -59,16 +65,12 @@ static void wifi_generic_enable(struct device *dev) { - DEVTREE_CONST struct drivers_wifi_generic_config *config = dev ? dev->chip_info : NULL; - - if (!config) - return; - #if !DEVTREE_EARLY - if (is_cnvi(dev)) - dev->ops = &wifi_cnvi_ops; + const struct device *parent = dev->bus->dev; + if (parent && parent->ops == &wifi_pcie_ops) + dev->ops = &wifi_generic_ops; else - dev->ops = &wifi_pcie_ops; + dev->ops = &wifi_cnvi_ops; #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/62746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Gerrit-Change-Number: 62746 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Eric Lai (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, John Zhao, Angel Pons, Nick Vaccaro, Patrick Rudolph, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/p2sb/p2sblib.c: https://review.coreboot.org/c/coreboot/+/62778/comment/ec5e1245_a142c99b PS3, Line 13: uint32_t low_bar, uint32_t high_bar > hm, maybe use one uint64_t instead? if i read this correctly, these two arguments are the lower and […] In this topic, just wondering would pci support 64 bit read/write 😎 -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 17 Mar 2022 14:53:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/intel/usb4/retimer: Change loglevel prefix
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62822 ) Change subject: driver/intel/usb4/retimer: Change loglevel prefix ...................................................................... driver/intel/usb4/retimer: Change loglevel prefix In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message in not support dpf ports. It's not error and changes the loglevel prefix to BIOS_INFO. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62822 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/usb4/retimer/retimer.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index 0c027eb..a13f79a 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -358,7 +358,7 @@ for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) { if (!config->dfp[dfp_port].power_gpio.pin_count) { - printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n", + printk(BIOS_WARNING, "%s: No DFP%1d power GPIO for %s\n", __func__, dfp_port, dev_path(dev)); continue; } -- To view, visit https://review.coreboot.org/c/coreboot/+/62822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73 Gerrit-Change-Number: 62822 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/hp/z220_series: Convert z220_sff_workstation into variant
by Felix Singer (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Damien Zammit, Edward O'Callaghan, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62808 ) Change subject: mb/hp/z220_series: Convert z220_sff_workstation into variant ...................................................................... Patch Set 2: (1 comment) File src/mainboard/hp/z220_series/Kconfig: https://review.coreboot.org/c/coreboot/+/62808/comment/8c0af121_6aeb8a6c PS2, Line 1: ## SPDX-License-Identifier: GPL-2.0-only > Happy to remove it if you prefer. Yes, please remove. We don't use license headers in Kconfig files anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/62808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Gerrit-Change-Number: 62808 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 14:44:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Damien Zammit Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/retimer: Change loglevel prefix
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62821 ) Change subject: soc/intel/alderlake/retimer: Change loglevel prefix ...................................................................... soc/intel/alderlake/retimer: Change loglevel prefix This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/retimer.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c index 09bf112..3fd9c2d 100644 --- a/src/soc/intel/alderlake/retimer.c +++ b/src/soc/intel/alderlake/retimer.c @@ -18,7 +18,7 @@ for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { if (i == typec_port) { - printk(BIOS_ERR, "USB Type-C %d mapped to EC port %d\n", typec_port, + printk(BIOS_INFO, "USB Type-C %d mapped to EC port %d\n", typec_port, ec_port); return ec_port; } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5 Gerrit-Change-Number: 62821 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/google/chromeec: Change loglevel prefix
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62823 ) Change subject: ec/google/chromeec: Change loglevel prefix ...................................................................... ec/google/chromeec: Change loglevel prefix In most boards, it doesn't write OEM_NAME in CBI to override the manufacturer name in the SMBIOS table. It' better use the "BIOS_INFO" than "BIOS_ERR" BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62823 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/ec/google/chromeec/ec_smbios.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec_smbios.c b/src/ec/google/chromeec/ec_smbios.c index aedcf85..0616c986 100644 --- a/src/ec/google/chromeec/ec_smbios.c +++ b/src/ec/google/chromeec/ec_smbios.c @@ -29,7 +29,7 @@ if (google_chromeec_cbi_get_oem_name(&oem_name[0], ARRAY_SIZE(oem_name)) < 0) { - printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n"); + printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n"); manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; } else { manuf = &oem_name[0]; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89 Gerrit-Change-Number: 62823 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC power control setting
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62627 ) Change subject: mb/google/brya/var/kinox: Modify 15W SOC power control setting ...................................................................... mb/google/brya/var/kinox: Modify 15W SOC power control setting Modify 15W SOC default power settings for kinox. - PL2 39W - PL4 100W - Psys_PL2 65W - Psys_imax_ma 5000ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62627 Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/ramstage.c 2 files changed, 69 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc index 58c4d79..681c764 100644 --- a/src/mainboard/google/brya/variants/kinox/Makefile.inc +++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc @@ -2,3 +2,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kinox/ramstage.c b/src/mainboard/google/brya/variants/kinox/ramstage.c new file mode 100644 index 0000000..aa805ce --- /dev/null +++ b/src/mainboard/google/brya/variants/kinox/ramstage.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 15000, 39000, 39000, 100000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 28000, 28000, 64000, 64000, 90000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 28000, 28000, 64000, 64000, 140000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 45, 45000, 45000, 95000, 95000, 125000 }, + { PCI_DID_INTEL_ADL_P_ID_4, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 45, 45000, 45000, 115000, 115000, 215000 }, + { PCI_DID_INTEL_ADL_P_ID_1, 45, 45000, 45000, 95000, 95000, 125000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ + { PCI_DID_INTEL_ADL_P_ID_10, 15, 65 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 65 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 65 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 230 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 230 }, + { PCI_DID_INTEL_ADL_P_ID_5, 45, 230 }, + { PCI_DID_INTEL_ADL_P_ID_4, 45, 230 }, + { PCI_DID_INTEL_ADL_P_ID_3, 45, 230 }, + { PCI_DID_INTEL_ADL_P_ID_1, 45, 230 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in kinox, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 5A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 5A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.63 = 300K / (300K + 169K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 5A = 75W + * For Type-C 20V, the Psys_pmax should be 20v x 5A = 100W + * For a barrel jack, the Psys_pmax should be 20v x 5A = 100W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 100W. Then IMVP9.1 can calculate the current system + * power = 100W * 5A / 5A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 5000, + .bj_volts_mv = 20000 +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 8 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Tim Wawrzynczak, John Zhao, Angel Pons, Nick Vaccaro, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/p2sb/p2sblib.c: https://review.coreboot.org/c/coreboot/+/62778/comment/8094f07e_70b690b1 PS3, Line 13: uint32_t low_bar, uint32_t high_bar hm, maybe use one uint64_t instead? if i read this correctly, these two arguments are the lower and upper half of a 64 bit BAR, so i wouldn't split it into two arguments -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 14:41:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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