coreboot-gerrit March 2022

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Change in coreboot[master]: soc/amd/cezanne: Add counter initializers
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62872 ) Change subject: soc/amd/cezanne: Add counter initializers ...................................................................... soc/amd/cezanne: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 92debe3..8c9e5a1 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -45,10 +45,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) { - const fsp_dxio_descriptor *fsp_dxio; - const fsp_ddi_descriptor *fsp_ddi; - size_t num_dxio; - size_t num_ddi; + const fsp_dxio_descriptor *fsp_dxio = NULL; + const fsp_ddi_descriptor *fsp_ddi = NULL; + size_t num_dxio = 0; + size_t num_ddi = 0; mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); -- To view, visit https://review.coreboot.org/c/coreboot/+/62872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 Gerrit-Change-Number: 62872 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Jon Murphy (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62903 to look at the new patch set (#5). Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... mb/google/skyrim: Add DXIO descriptors Add Skyrim DXIO descriptors using info from AMD and skyrim board schematics. BUG=b:225179599 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 --- M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 3 files changed, 116 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62903/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Add counter initializers
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62871 ) Change subject: soc/amd/picasso: Add counter initializers ...................................................................... soc/amd/picasso: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/picasso/fsp_s_params.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index af7de37..2e10555 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -92,10 +92,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg) { - const fsp_dxio_descriptor *fsp_dxio; - const fsp_ddi_descriptor *fsp_ddi; - size_t num_dxio; - size_t num_ddi; + const fsp_dxio_descriptor *fsp_dxio = NULL; + const fsp_ddi_descriptor *fsp_ddi = NULL; + size_t num_dxio = 0; + size_t num_ddi = 0; mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); -- To view, visit https://review.coreboot.org/c/coreboot/+/62871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Gerrit-Change-Number: 62871 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina: Add counter initializers
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62863 ) Change subject: soc/amd/sabrina: Add counter initializers ...................................................................... soc/amd/sabrina: Add counter initializers Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/fsp_m_params.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/soc/amd/sabrina/fsp_m_params.c b/src/soc/amd/sabrina/fsp_m_params.c index f069ba8..8a83008 100644 --- a/src/soc/amd/sabrina/fsp_m_params.c +++ b/src/soc/amd/sabrina/fsp_m_params.c @@ -47,10 +47,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_M_CONFIG *mcfg) { - const fsp_dxio_descriptor *fsp_dxio; - const fsp_ddi_descriptor *fsp_ddi; - size_t num_dxio; - size_t num_ddi; + const fsp_dxio_descriptor *fsp_dxio = NULL; + const fsp_ddi_descriptor *fsp_ddi = NULL; + size_t num_dxio = 0; + size_t num_ddi = 0; mainboard_get_dxio_ddi_descriptors(&fsp_dxio, &num_dxio, &fsp_ddi, &num_ddi); -- To view, visit https://review.coreboot.org/c/coreboot/+/62863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Gerrit-Change-Number: 62863 Gerrit-PatchSet: 8 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62903 ) Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... Patch Set 4: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62903/comment/84ee5c8d_cb9fd28e PS3, Line 9: bouard board https://review.coreboot.org/c/coreboot/+/62903/comment/44bb5d86_4d1078d0 PS3, Line 10: shematics schematics https://review.coreboot.org/c/coreboot/+/62903/comment/d7dec241_527268fa PS3, Line 13: TEST=Builds just a build test is likely not sufficient; at least i'd prefer to have it verified on hardware that all pcie devices end up working File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/62903/comment/73786acd_121b0e56 PS3, Line 49: //.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} // TODO: uncomment this when PSPP is working the commented out lines can be dropped for now. i also expect that we'll need different values here when pspp is working; probably {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} https://review.coreboot.org/c/coreboot/+/62903/comment/b0329b0d_69c50986 PS3, Line 54: .start_logical_lane = 0, the engine is unused, but the lanes overlap with the dxio descriptors before this one File src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/62903/comment/4936d5d2_fbddaf38 PS3, Line 10: #define WLAN_DEVFN PCIE_GPP_2_0_DEVFN : #define SD_DEVFN PCIE_GPP_2_1_DEVFN i'm not certain if those device functions need to be swapped. there are requirements for the assignment of pcie device functions to root ports depending on the logical lane numbers within all devices with the same link width -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 17:38:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Jon Murphy (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Raul Rangel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62903 to look at the new patch set (#4). Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... mb/google/skyrim: Add DXIO descriptors Add Skyrim DXIO descriptors using info from AMD and skyrim bouard shematics. BUG=b:225179599 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 --- M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 3 files changed, 116 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62903/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Felix Held (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, John Zhao, Angel Pons, Nick Vaccaro, Eric Lai, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 17 Mar 2022 17:28:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Configure TCSS access through IOE P2SB
by Subrata Banik (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: John Zhao, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Configure TCSS access through IOE P2SB ...................................................................... Patch Set 5: -Code-Review (1 comment) Patchset: PS5: Very nice thought Tim -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 5 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 17 Mar 2022 17:27:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init
by Karthik Ramasubramanian (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Jon Murphy, Rob Barnes, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62880 ) Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/62880/comment/d85d0859_41a91488 PS1, Line 348: PSP_POSTCODES_ON_ESPI Mohan/Avinash, Does PSP use ESPI to write postcodes by default? Also does Cezanne use Soft Fuse Bit 15 if this config is enabled? -- To view, visit https://review.coreboot.org/c/coreboot/+/62880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Gerrit-Change-Number: 62880 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Mohan Viswanathan Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 17 Mar 2022 17:27:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by build bot (Jenkins) (Code Review) 17 Mar '22

17 Mar '22

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62903 ) Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/skyrim/port_descriptors.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144201): https://review.coreboot.org/c/coreboot/+/62903/comment/2f8b5144_a751464d PS3, Line 22: //.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} // TODO: uncomment this when PSPP is working line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144201): https://review.coreboot.org/c/coreboot/+/62903/comment/803ff07b_77b2aa3b PS3, Line 49: //.port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} // TODO: uncomment this when PSPP is working line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 17 Mar 2022 17:24:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022