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Change subject: soc/mediatek/mt8195: Add early init support
......................................................................
soc/mediatek/mt8195: Add early init support
Add early init support for MT8195 platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac
---
M src/mainboard/google/cherry/bootblock.c
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/bootblock.c
M src/soc/mediatek/mt8195/include/soc/memlayout.ld
4 files changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/63020/2
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Change subject: soc/mediatek: Add mtk_early_init for passing data across sessions
......................................................................
soc/mediatek: Add mtk_early_init for passing data across sessions
Passing pcie timestamp from bootblock stage to ram stage, it can be used
for other modules if they needs to passing data across sessions.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a
---
M src/soc/mediatek/common/Kconfig
A src/soc/mediatek/common/early_init.c
A src/soc/mediatek/common/include/soc/early_init.h
3 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63019/2
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Change subject: mb/google/cherry: Add PCIe domain support for dojo
......................................................................
mb/google/cherry: Add PCIe domain support for dojo
Add override device tree for dojo and add PCIe domain support.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972
---
M src/mainboard/google/cherry/Kconfig
A src/mainboard/google/cherry/variants/dojo/overridetree.cb
2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62360/20
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/cherry: Pre-initialize PCIe at the bootblock stage
......................................................................
mb/google/cherry: Pre-initialize PCIe at the bootblock stage
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.
Instead of asserting PERST# right before PCIe initialization and wait
for 100ms, assert the pin in bootblock stage so that the extra 100ms
delay could be avoided.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
---
M src/mainboard/google/cherry/bootblock.c
M src/soc/mediatek/mt8195/Makefile.inc
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62359/20
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62362 )
Change subject: treewide: Drop unused Kconfig symbols
......................................................................
Patch Set 7: Code-Review+2
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Change subject: device: Set set_resources message for device_operations function
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Same as change-set Ifee7479c69cf16025dbd4e3924056ed7f8e253cf?
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Change subject: mb/google/brya: Set pciexp_hotplug_dummy_ops.set_resources as no-op
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Same as change-set I2cd7413b2c8d1c8f5ac0f3b77747839ddacb241b?
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Change subject: treewide: Drop unused Kconfig symbols
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62362/comment/b471a14d_f55de82d
PS7, Line 7: treewide
Just use `src`?
https://review.coreboot.org/c/coreboot/+/62362/comment/040f672b_fd876f23
PS7, Line 8:
If easily doable, maybe list all the symbols in the body.
https://review.coreboot.org/c/coreboot/+/62362/comment/627cd035_5b4d818b
PS7, Line 11: Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Signing of once should be enough. ;-)
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Change subject: treewide: Drop unused Kconfig symbols
......................................................................
Patch Set 7: Code-Review+1
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