coreboot-gerrit March 2022

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Change in coreboot[master]: src/arch/arm/include/armv7/arch/cache.h:
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Athanasios Kastoras. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63125 ) Change subject: src/arch/arm/include/armv7/arch/cache.h: ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63125/comment/e7e345fb_1bfb1c57 PS1, Line 9: Remove unnecessary whitespace before closing parenthesis at inline assembly statements : on lines 237 and 252 would be good if you could wrap the commit message to 72 chars -- To view, visit https://review.coreboot.org/c/coreboot/+/63125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa8174837ff7d20a8217d75e2028a62a381aede Gerrit-Change-Number: 63125 Gerrit-PatchSet: 1 Gerrit-Owner: Athanasios Kastoras <thanoskastoras(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Athanasios Kastoras <thanoskastoras(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 23:57:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/crota: Add memory config for crota
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63137 ) Change subject: mb/google/brya/variants/crota: Add memory config for crota ...................................................................... mb/google/brya/variants/crota: Add memory config for crota Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/crota/Makefile.inc A src/mainboard/google/brya/variants/crota/memory.c 2 files changed, 103 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/crota/Makefile.inc b/src/mainboard/google/brya/variants/crota/Makefile.inc index 6c29346..7d1f886 100644 --- a/src/mainboard/google/brya/variants/crota/Makefile.inc +++ b/src/mainboard/google/brya/variants/crota/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/crota/memory.c b/src/mainboard/google/brya/variants/crota/memory.c new file mode 100644 index 0000000..659d214 --- /dev/null +++ b/src/mainboard/google/brya/variants/crota/memory.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = { 40, 36, 35, 35, 35 }, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, }, + .dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, }, + }, + .ddr2 = { + .dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, }, + .dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, }, + }, + .ddr3 = { + .dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, }, + .dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, }, + .dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, }, + }, + .ddr5 = { + .dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, }, + .dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, }, + }, + .ddr6 = { + .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, }, + .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Gerrit-Change-Number: 63137 Gerrit-PatchSet: 4 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Jesper Lin <jesper_lin(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "mb/google/brya/var/kano: adjust I2C3 speed"
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63168 ) Change subject: Revert "mb/google/brya/var/kano: adjust I2C3 speed" ...................................................................... Revert "mb/google/brya/var/kano: adjust I2C3 speed" This reverts commit 65aaccda5910e9c74aaa2a44ea84119d9476c902. Reason: 1. Fix firmware messages show [ERROR] dw_i2c:invalid bus speed 390000 2. Measure DVT I2C3 speed < 400KHz. BUG=b:215095284 TEST=There isn't ERROR messages and verify I2C3 speed < 400KHz. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 41c3cf2..5d7e30a 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -56,7 +56,7 @@ .data_hold_time_ns = 50, }, .i2c[3] = { - .speed = 390000, + .speed = I2C_SPEED_FAST, .rise_time_ns = 650, .fall_time_ns = 400, .data_hold_time_ns = 50, -- To view, visit https://review.coreboot.org/c/coreboot/+/63168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Gerrit-Change-Number: 63168 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... soc/intel/alderlake: Log CSE RO write protection info for ADL The patch logs CSE RO's write protection information for Alder Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/me.c 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index ea94902..31b09da 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -2,6 +2,7 @@ #include <bootstate.h> #include <intelblocks/cse.h> +#include <intelblocks/spi.h> #include <console/console.h> #include <soc/me.h> #include <stdint.h> @@ -90,6 +91,25 @@ } __packed fields; }; +static void log_me_ro_write_protection_info(bool mfg_mode) +{ + bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); + + printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", + cse_ro_wp_en ? "YES" : "NO"); + + if (cse_ro_wp_en) { + uint32_t base, limit; + spi_get_wp_cse_ro_range(&base, &limit); + printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", + base, limit); + } + + /* If EOM is disabled, but CSE RO is not write protected, log error */ + if (!mfg_mode && !cse_ro_wp_en) + printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); +} + static void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -161,6 +181,9 @@ hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + log_me_ro_write_protection_info(!!hfsts1.fields.mfg_mode); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 14: (4 comments) Patchset: PS14: haven't looked at the FUSE_STATUS_* definitions yet File src/soc/amd/common/block/psp/psb.c: https://review.coreboot.org/c/coreboot/+/60968/comment/0b372559_ffde5672 PS14, Line 12: #define PSB_HSTI_STATUS_OFFSET 0x10998 the PSB_HSTI_STATUS_OFFSET definition can be dropped; already defined as CORE_2_PSP_MSG_38_OFFSET and used in soc_read_c2p38 which is called from psb_enable https://review.coreboot.org/c/coreboot/+/60968/comment/15f09f62_9ea0a780 PS14, Line 17: #define PSB_FUSING_READY_MASK 0x100 i'd change this to #define PSB_FUSING_READY BIT(8), since it's only one bit and not a bit maskwith multiple bits https://review.coreboot.org/c/coreboot/+/60968/comment/9e6f40a2_2f035a00 PS14, Line 19: #define PSB_TEST_STATUS_FUSE_READ_ERR 0x3e : #define PSB_TEST_STATUS_BIOS_KEY_BAD_USAGE 0x81 : #define PSB_TEST_STATUS_BIOS_RTM_SIG_NOENT 0x82 : #define PSB_TEST_STATUS_BIOS_RTM_COPY_ERR 0x83 : #define PSB_TEST_STATUS_BIOS_RTM_BAD_SIG 0x84 : #define PSB_TEST_STATUS_BIOS_KEY_BAD_SIG 0x85 : #define PSB_TEST_STATUS_PLATFORM_BAD_ID 0x86 : #define PSB_TEST_STATUS_BIOS_COPY_BIT_UNSET 0x87 : #define PSB_TEST_STATUS_BIOS_CA_BAD_SIG 0x8a : #define PSB_TEST_STATUS_BIOS_CA_BAD_USAGE 0x8b : #define PSB_TEST_STATUS_BIOS_KEY_BAD_REVISION 0x8c is this soc specific? at least a comment in the reference code suggest this -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 14 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Mar 2022 23:54:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63235 ) Change subject: soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls ...................................................................... soc/amd/sabrina/makefile: drop multilevel option in amdfwtool calls Since Sabrina uses the image slot header (ISH) that depends on the AMD A/B recovery scheme that depends on the multi-level PSP directory support, the multi-level support gets automatically selected by passing Sabrina as SoC name to amdfwtool, so passing the --multilevel command line switch to amdfwtool isn't needed. TEST=Timeless build results in identical binary for chausie Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 --- M src/soc/amd/sabrina/Makefile.inc 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/63235/1 diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index b504589..b7b538e 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -232,7 +232,6 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(SABRINA_FWM_POSITION)) \ - --multilevel \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) @@ -250,7 +249,6 @@ $(OPT_APOB_NV_BASE) \ --location $(shell printf "%#x" $(SABRINA_FW_A_POSITION)) \ --anywhere \ - --multilevel \ --output $@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom @@ -262,7 +260,6 @@ $(OPT_APOB_NV_BASE) \ --location $(shell printf "%#x" $(SABRINA_FW_B_POSITION)) \ --anywhere \ - --multilevel \ --output $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/63235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 Gerrit-Change-Number: 63235 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltage
by Karthik Ramasubramanian (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63234 ) Change subject: soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b Gerrit-Change-Number: 63234 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 30 Mar 2022 23:42:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool call
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63189 ) Change subject: soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool call ...................................................................... soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool call Now that the amdfwtool support for Sabrina is in place, change the SoC name parameter passed to amdfwtool from Cezanne to Sabrina. The fw.cfg file still points to the Cezanne binaries, but since commit 9cb0a05dfb308323a5b3df1a25fa66b35ecfcdd6 (soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig config file in the build. As soon as the Sabrina PSP binaries are available in 3rparty/amd_blobs, the fw.cfg file will be updated to use the correct ones for Sabrina. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/sabrina/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index 89ed88d..b504589 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -211,7 +211,7 @@ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --soc-name "Cezanne" \ + --soc-name "Sabrina" \ --flashsize $(CONFIG_ROM_SIZE) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/63189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609 Gerrit-Change-Number: 63189 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type
by Karthik Ramasubramanian (Code Review) 31 Mar '22

31 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63233 ) Change subject: soc/amd/sabrina/i2c: handle all I2C pads as I23C pad type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Gerrit-Change-Number: 63233 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 30 Mar 2022 23:42:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handling
by Felix Held (Code Review) 31 Mar '22

31 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63188 ) Change subject: soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handling ...................................................................... soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handling The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the Cezanne Kconfig, so drop this from the Sabrina makefile. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/sabrina/Makefile.inc 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index 3271c9f..89ed88d 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -111,10 +111,6 @@ PSP_SOFTFUSE_BITS += 29 endif -ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) -PSP_SOFTFUSE_BITS += 58 -endif - # Use additional Soft Fuse bits specified in Kconfig PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c Gerrit-Change-Number: 63188 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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