coreboot-gerrit November 2022

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[S] Change in coreboot[master]: device/xhci: Factor out `struct xhci_usb_info`
by Martin Roth (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Robert Zieba, Raul Rangel, Karthik Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67934 ) Change subject: device/xhci: Factor out `struct xhci_usb_info` ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Gerrit-Change-Number: 67934 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 23:14:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER
by Caveh Jalali (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Jason Nien, Caveh Jalali, Kapil Porwal, Nick Vaccaro, Martin Roth, Boris Mittelberg. Hello Tarun Tuli, Subrata Banik, Jason Nien, Kapil Porwal, Nick Vaccaro, Martin Roth, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69374 to look at the new patch set (#3). Change subject: ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER ...................................................................... ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all references. BUG=b:216485035,b:258126464 BRANCH=none TEST=none Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/auron/ec.h M src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h M src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h M src/mainboard/google/cyan/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/shotzo/include/variant/ec.h M src/mainboard/google/glados/ec.h M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/link/ec.h M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/rambi/ec.h M src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/reef/variants/sand/include/variant/ec.h M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/ec.h M src/mainboard/google/slippy/ec.h M src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/kblrvp/ec.h M src/mainboard/intel/kunimitsu/ec.h M src/mainboard/intel/strago/ec.h 23 files changed, 19 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/69374/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Gerrit-Change-Number: 69374 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality
by Martin Roth (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Arthur Heymans, Robert Zieba, Nico Huber, Angel Pons, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 ) Change subject: cpu/x86/smm: Add PCI BAR store functionality ...................................................................... Patch Set 7: Code-Review+2 (2 comments) File src/cpu/x86/smm/pci_bar_store.c: https://review.coreboot.org/c/coreboot/+/67931/comment/1dc05624_24c5c650 PS7, Line 18: nit: extra line https://review.coreboot.org/c/coreboot/+/67931/comment/9ef08e8f_f5c37b9a PS7, Line 20: if (num_devices > num_slots) { : printk(BIOS_ERR, "Failed to store PCI BARs, number of devices exceeds slots\n"); : return false; : } nit: Would it make sense to do this check inside the for loop so that it can store what bars it can, especially since a device could be skipped if it's not in the resource list. Can this be turned into a static assert so it fails at build time? Use a regular assert so that it halts if fatal asserts are enabled? Feel free to look at this in a follow-on if any of it makes sense. -- To view, visit https://review.coreboot.org/c/coreboot/+/67931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37 Gerrit-Change-Number: 67931 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Nov 2022 23:13:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vboot: Add VBOOT_CBFS_INTEGRATION support
by Julius Werner (Code Review) 08 Nov '22

08 Nov '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66909 ) ( 25 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support ...................................................................... vboot: Add VBOOT_CBFS_INTEGRATION support This patch introduces support signing and verification of firmware slots using CBFS metadata hash verification method for faster initial verification. To have complete verification, CBFS_VERIFICATION should also be enabled, as metadata hash covers only files metadata, not their contents. This patch also adapts mainboards and SoCs to new vboot reset requirements. TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/cbfs_glue.h M src/lib/cbfs.c M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/cherry/Makefile.inc M src/mainboard/google/corsola/Makefile.inc M src/mainboard/google/geralt/Makefile.inc M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/common.c M src/security/vboot/vboot_common.c M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/soc/mediatek/mt8173/Makefile.inc 13 files changed, 126 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/include/cbfs_glue.h b/src/include/cbfs_glue.h index d4fe367..99dc48d 100644 --- a/src/include/cbfs_glue.h +++ b/src/include/cbfs_glue.h @@ -13,11 +13,17 @@ * safety, we only need to verify the metadata hash in the initial stage and can assume it stays * valid in later stages. If TOCTOU safety is required, we may need them in every stage to * reverify metadata that had to be reloaded from flash (e.g. because it didn't fit the mcache). + * Moreover, if VBOOT_CBFS_INTEGRATION and verification are both enabled, then hashing functions + * are required during verification stage. * Note that this only concerns metadata hashing -- file access functions may still link hashing * routines independently for file data hashing. */ #define CBFS_ENABLE_HASHING (CONFIG(CBFS_VERIFICATION) && \ - (CONFIG(TOCTOU_SAFETY) || ENV_INITIAL_STAGE)) + (CONFIG(TOCTOU_SAFETY) || ENV_INITIAL_STAGE || \ + (CONFIG(VBOOT_CBFS_INTEGRATION) && \ + (verification_should_run() || \ + (verstage_should_load() && \ + CONFIG(VBOOT_RETURN_FROM_VERSTAGE)))))) #define CBFS_HASH_HWCRYPTO vboot_hwcrypto_allowed() #define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 4f2d9ca..d2829d1 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -12,6 +12,7 @@ #include <list.h> #include <metadata_hash.h> #include <security/tpm/tspi/crtm.h> +#include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <stdlib.h> #include <string.h> @@ -57,7 +58,10 @@ RO CBFS would have been caught when building the mcache in cbfs_get boot_device(). (Note that TOCTOU_SAFETY implies !NO_CBFS_MCACHE.) */ assert(cbd == vboot_get_cbfs_boot_device()); - die("TODO: set metadata_hash to RW metadata hash here.\n"); + if (!CONFIG(VBOOT) + || vb2api_get_metadata_hash(vboot_get_context(), &metadata_hash) + != VB2_SUCCESS) + die("Failed to get RW metadata hash"); } err = cbfs_lookup(&cbd->rdev, name, mdata, &data_offset, metadata_hash); } @@ -160,8 +164,14 @@ ERROR("'%s' does not have a file hash!\n", mdata->h.filename); return true; } - if (vb2_hash_verify(vboot_hwcrypto_allowed(), buffer, size, hash)) { + + vb2_error_t rv = vb2_hash_verify(vboot_hwcrypto_allowed(), buffer, size, hash); + if (rv != VB2_SUCCESS) { ERROR("'%s' file hash mismatch!\n", mdata->h.filename); + if (CONFIG(VBOOT_CBFS_INTEGRATION) && !vboot_recovery_mode_enabled() + && vboot_logic_executed()) + vboot_fail_and_reboot(vboot_get_context(), VB2_RECOVERY_FW_BODY, + rv); return true; } } diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 601b485..84600b6 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -12,6 +12,7 @@ romstage-y += boardid.c romstage-y += chromeos.c romstage-y += regulator.c +romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index e1e363c..4edbd38 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -10,6 +10,7 @@ romstage-y += boardid.c romstage-y += chromeos.c romstage-y += regulator.c +romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index 30ee6c1..d11f6ba 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -10,6 +10,7 @@ romstage-y += boardid.c romstage-y += chromeos.c romstage-y += regulator.c +romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/geralt/Makefile.inc b/src/mainboard/google/geralt/Makefile.inc index 85748dd..006b4f2 100644 --- a/src/mainboard/google/geralt/Makefile.inc +++ b/src/mainboard/google/geralt/Makefile.inc @@ -9,6 +9,7 @@ romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += regulator.c +romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a36510d..93e1845 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -35,6 +35,20 @@ help Have two update partitions beside the RO partition. +config VBOOT_CBFS_INTEGRATION + bool "Enable vboot and CBFS integration" + default n + depends on VBOOT_SLOTS_RW_A + depends on CBFS_VERIFICATION + help + Say yes here to enable cryptographic verification of RW slots CBFS + metadata. This will replace body hash verification. + + This option enables integration of vboot and CBFS. Verification of RW + slots is performed by calculation of their CBFS metadata hash. + It also requires CBFS_VERIFICATION to be enabled, so that CBFS files + contents are correctly verified. + config VBOOT_VBNV_CMOS bool default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index bd73871..e4771dd 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -61,6 +61,7 @@ verstage-y += vbnv.c romstage-y += vbnv.c ramstage-y += vbnv.c +postcar-y += vbnv.c romstage-$(CONFIG_VBOOT_EARLY_EC_SYNC) += ec_sync.c @@ -68,16 +69,19 @@ verstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c romstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS) += vbnv_cmos.c bootblock-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c +postcar-$(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH) += vbnv_flash.c bootblock-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c verstage-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c romstage-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c ramstage-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c +postcar-$(CONFIG_VBOOT_VBNV_FLASH) += vbnv_flash.c bootblock-y += vboot_loader.c romstage-y += vboot_loader.c diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 7f1aee1..1703933 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -63,8 +63,16 @@ if (ret) return ret; - /* Truncate area to the size that was actually signed by vboot. */ - return rdev_chain(fw, fw, 0, vb2api_get_firmware_size(ctx)); + /* + * Truncate area to the size that was actually signed by vboot. + * It is only required for old verification mechanism calculating full body hash. + * New verification mechanism uses signature with zero data size, so truncation + * is not possible. + */ + if (!CONFIG(VBOOT_CBFS_INTEGRATION)) + return rdev_chain(fw, fw, 0, vb2api_get_firmware_size(ctx)); + + return 0; } static void vboot_setup_cbmem(int unused) diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 8ecb5d8..dd611d1 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -11,6 +11,11 @@ void vboot_save_data(struct vb2_context *ctx) { + if (!verification_should_run() && !(ENV_ROMSTAGE && CONFIG(VBOOT_EARLY_EC_SYNC)) + && (ctx->flags + & (VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED | VB2_CONTEXT_SECDATA_KERNEL_CHANGED))) + die("TPM writeback in " ENV_STRING "?"); + if (ctx->flags & VB2_CONTEXT_SECDATA_FIRMWARE_CHANGED && (CONFIG(VBOOT_MOCK_SECDATA) || tlcl_lib_init() == VB2_SUCCESS)) { printk(BIOS_INFO, "Saving secdata firmware\n"); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 0acb349..7cda690 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -28,15 +28,32 @@ static void after_verstage(void) { + struct vb2_hash *metadata_hash = NULL; + struct vb2_context *ctx = NULL; + + if (CONFIG(VBOOT_CBFS_INTEGRATION)) { + ctx = vboot_get_context(); + vb2_error_t rv = vb2api_get_metadata_hash(ctx, &metadata_hash); + if (rv) + vboot_fail_and_reboot(ctx, VB2_RECOVERY_FW_PREAMBLE, rv); + } + vboot_executed = 1; /* Mark verstage execution complete. */ const struct cbfs_boot_device *cbd = vboot_get_cbfs_boot_device(); if (!cbd) /* Can't initialize RW CBFS in recovery mode. */ return; - enum cb_err err = cbfs_init_boot_device(cbd, NULL); /* TODO: RW hash */ - if (err && err != CB_CBFS_CACHE_FULL) /* TODO: -> recovery? */ - die("RW CBFS initialization failure: %d", err); + enum cb_err err = cbfs_init_boot_device(cbd, metadata_hash); + if (err && err != CB_CBFS_CACHE_FULL) { + if (CONFIG(VBOOT_CBFS_INTEGRATION)) { + printk(BIOS_ERR, "RW CBFS initialization failed: %d\n", err); + /* CBFS error code does not fit in subcode. Use only lowest byte. */ + vboot_fail_and_reboot(ctx, VB2_RECOVERY_FW_BODY, err & 0xFF); + } else { + die("RW CBFS initialization failure: %d", err); + } + } } void vboot_run_logic(void) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 660b7da..98a044c 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -54,7 +54,7 @@ return VB2_SUCCESS; } -static int handle_digest_result(void *slot_hash, size_t slot_hash_sz) +static vb2_error_t handle_digest_result(void *slot_hash, size_t slot_hash_sz) { int is_resume; @@ -63,14 +63,14 @@ * vboot_retrieve_hash(), if Chrome EC is not enabled then return. */ if (!CONFIG(EC_GOOGLE_CHROMEEC)) - return 0; + return VB2_SUCCESS; /* * Nothing to do since resuming on the platform doesn't require * vboot verification again. */ if (!CONFIG(RESUME_PATH_SAME_AS_BOOT)) - return 0; + return VB2_SUCCESS; /* * Assume that if vboot doesn't start in bootblock verified @@ -78,7 +78,7 @@ * lives in RO CBFS. */ if (!CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - return 0; + return VB2_SUCCESS; is_resume = platform_is_resuming(); @@ -92,12 +92,12 @@ if (vboot_retrieve_hash(saved_hash, saved_hash_sz)) { printk(BIOS_ERR, "Couldn't retrieve saved hash.\n"); - return -1; + return VB2_ERROR_UNKNOWN; } if (memcmp(saved_hash, slot_hash, slot_hash_sz)) { printk(BIOS_ERR, "Hash mismatch on resume.\n"); - return -1; + return VB2_ERROR_UNKNOWN; } } else if (is_resume < 0) printk(BIOS_ERR, "Unable to determine if platform resuming.\n"); @@ -111,10 +111,10 @@ * lead to a reboot loop. The consequence of this is that * we will most likely fail resuming because of EC issues or * the hash digest not matching. */ - return 0; + return VB2_SUCCESS; } - return 0; + return VB2_SUCCESS; } static vb2_error_t hash_body(struct vb2_context *ctx, @@ -179,10 +179,7 @@ timestamp_add_now(TS_HASH_BODY_END); - if (handle_digest_result(hash_digest, hash_digest_sz)) - return VB2_ERROR_UNKNOWN; - - return VB2_SUCCESS; + return handle_digest_result(hash_digest, hash_digest_sz); } static uint32_t extend_pcrs(struct vb2_context *ctx) @@ -236,16 +233,10 @@ ctx->flags |= VB2_CONTEXT_EC_TRUSTED; } -/** - * Verify and select the firmware in the RW image - * - * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage). - * when per-stage verification is ready. - */ +/* Verify and select the firmware in the RW image */ void verstage_main(void) { struct vb2_context *ctx; - struct region_device fw_body; vb2_error_t rv; timestamp_add_now(TS_VBOOT_START); @@ -326,7 +317,6 @@ extend_pcrs(ctx); /* ignore failures */ goto verstage_main_exit; } - vboot_save_and_reboot(ctx, rv); } @@ -345,12 +335,22 @@ vboot_save_and_reboot(ctx, rv); printk(BIOS_INFO, "Phase 4\n"); - rv = vboot_locate_firmware(ctx, &fw_body); - if (rv) - die_with_post_code(POST_INVALID_ROM, - "Failed to read FMAP to locate firmware"); + if (CONFIG(VBOOT_CBFS_INTEGRATION)) { + struct vb2_hash *metadata_hash; + rv = vb2api_get_metadata_hash(ctx, &metadata_hash); + if (rv == VB2_SUCCESS) + rv = handle_digest_result(metadata_hash->raw, + vb2_digest_size(metadata_hash->algo)); + } else { + struct region_device fw_body; + rv = vboot_locate_firmware(ctx, &fw_body); + if (rv) + die_with_post_code(POST_INVALID_ROM, + "Failed to read FMAP to locate firmware"); - rv = hash_body(ctx, &fw_body); + rv = hash_body(ctx, &fw_body); + } + if (rv) vboot_save_and_reboot(ctx, rv); vboot_save_data(ctx); diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index e824e54..7688ecf 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -46,6 +46,7 @@ romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c +romstage-y += ../common/wdt.c ../common/reset.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/rtc.c rtc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/66909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca Gerrit-Change-Number: 66909 Gerrit-PatchSet: 27 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
by Martin Roth (Code Review) 08 Nov '22

08 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69090 ) Change subject: soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions ...................................................................... soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/cpx/upd_display.c R src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/skx/upd_display.c M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 7 files changed, 37 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index e5a5963..bacbd6f 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -19,5 +19,6 @@ subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include +CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/include/soc/fsp_upd.h endif ## XEON_SP_COMMON_BASE diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 0cd267b..d2a1583 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -16,8 +16,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp -CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h - cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index efdce78..6ce5ef5 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -154,7 +154,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - FSPM_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; const struct device *dev; const config_t *config = config_of_soc(); diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c index ae5eeda..33807d3 100644 --- a/src/soc/intel/xeon_sp/cpx/upd_display.c +++ b/src/soc/intel/xeon_sp/cpx/upd_display.c @@ -12,8 +12,8 @@ const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { - const FSPM_CONFIG *new; - const FSPM_CONFIG *old; + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; old = &fspm_old_upd->FspmConfig; new = &fspm_new_upd->FspmConfig; @@ -31,8 +31,8 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - const FSPS_CONFIG *new; - const FSPS_CONFIG *old; + const FSP_S_CONFIG *new; + const FSP_S_CONFIG *old; old = &fsps_old_upd->FspsConfig; new = &fsps_new_upd->FspsConfig; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/include/soc/fsp_upd.h similarity index 61% rename from src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h rename to src/soc/intel/xeon_sp/include/soc/fsp_upd.h index 55b2e99..15ce96f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h +++ b/src/soc/intel/xeon_sp/include/soc/fsp_upd.h @@ -3,7 +3,10 @@ #ifndef _FSP_UPD_H_ #define _FSP_UPD_H_ -/* Rename the FSP UPD structs to what they were historically called on other platforms. */ +/* + * Intel FSPs of XEON server platforms define FSPX_CONFIG + * instead of FSP_X_CONFIG, which is expected by coreboot. + */ #define FSP_T_CONFIG FSPT_CONFIG #define FSP_M_CONFIG FSPM_CONFIG #define FSP_S_CONFIG FSPS_CONFIG diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c index 84105dd6..c718a58 100644 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ b/src/soc/intel/xeon_sp/skx/upd_display.c @@ -32,8 +32,8 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - const FSPS_CONFIG *new; - const FSPS_CONFIG *old; + const FSP_S_CONFIG *new; + const FSP_S_CONFIG *old; old = &fsps_old_upd->FspsConfig; new = &fsps_new_upd->FspsConfig; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index 0de0fa1..066c2ae 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -553,7 +553,7 @@ /** Offset 0x01E0 **/ UINT8 ReservedMemoryInitUpd[16]; -} FSP_M_CONFIG; +} FSPM_CONFIG; /** Fsp M UPD Configuration **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/69090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Gerrit-Change-Number: 69090 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/soc/intel/mtl: Print the correct CPU ID for A2
by Martin Roth (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Jyotsna Shridharan, Ravishankar Sarawadi, Kapil Porwal, Angel Pons, Raj Astekar. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69110 ) Change subject: src/soc/intel/mtl: Print the correct CPU ID for A2 ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/69110/comment/e5090408_a68d37d6 PS1, Line 20: CPUID_METEORLAKE_A0_2 > Should the macro be renamed? That seems reasonable. Please change to CPUID_METEORLAKE_A2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6296638c303f2581eca4bae8d0ec40ed19565c17 Gerrit-Change-Number: 69110 Gerrit-PatchSet: 1 Gerrit-Owner: Jyotsna Shridharan <jyotsna.shridharan(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jyotsna Shridharan <jyotsna.shridharan(a)intel.corp-partner.google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jyotsna Shridharan <jyotsna.shridharan(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 22:53:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/cbfstool/bpdt_formats: Fix memory leak issues
by Martin Roth (Code Review) 08 Nov '22

08 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68986 ) Change subject: util/cbfstool/bpdt_formats: Fix memory leak issues ...................................................................... util/cbfstool/bpdt_formats: Fix memory leak issues The functions create_bpdt_hdr and create_cse_layout in bpdt_1_6.c are defined to return pointers but not integers as was previouly implemented. Reported-by: Coverity(CID:1469323) Reported-by: Coverity(CID:1469353) Signed-off-by: Solomon Alan-Dei <alandei.solomon(a)gmail.com> Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M util/cbfstool/bpdt_formats/bpdt_1_6.c 1 file changed, 22 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/util/cbfstool/bpdt_formats/bpdt_1_6.c b/util/cbfstool/bpdt_formats/bpdt_1_6.c index b894936..c5cedd3 100644 --- a/util/cbfstool/bpdt_formats/bpdt_1_6.c +++ b/util/cbfstool/bpdt_formats/bpdt_1_6.c @@ -69,7 +69,7 @@ h->fit_tool_version.build = 0; h->fit_tool_version.hotfix = 0; - return 0; + return h; } static void print_bpdt_hdr(const bpdt_hdr_ptr ptr) @@ -159,7 +159,7 @@ l->bp3_size = r[BP3].size; l->checksum = 0; /* unused */ - return 0; + return l; } static void print_cse_layout(const cse_layout_ptr ptr) -- To view, visit https://review.coreboot.org/c/coreboot/+/68986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb78d94be7a75a25ad954f062e9e52b1f0b921dc Gerrit-Change-Number: 68986 Gerrit-PatchSet: 3 Gerrit-Owner: Solomon Alan-Dei <alandei.solomon(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/ti/am335x/cbmem.c: Use MiB macro
by 9elements QA (Code Review) 08 Nov '22

08 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61332 ) Change subject: soc/ti/am335x/cbmem.c: Use MiB macro ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134876 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134875 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134874 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134873 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134872 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134871 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134870 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134869 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134868 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134867 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134866 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134865 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134864 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134863 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134862 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134861 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/61332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49 Gerrit-Change-Number: 61332 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 22:50:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add fingerprint SPI
by Eran Mitrani (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Subrata Banik, Kapil Porwal, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66992 to look at the new patch set (#20). Change subject: mb/google/rex: Add fingerprint SPI ...................................................................... mb/google/rex: Add fingerprint SPI Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/rex0/gpio.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 3 files changed, 38 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/66992/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/66992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Gerrit-Change-Number: 66992 Gerrit-PatchSet: 20 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Add fingerprint SPI
by Eran Mitrani (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Subrata Banik, Kapil Porwal, Eric Lai. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66992 ) Change subject: mb/google/rex: Add fingerprint SPI ...................................................................... Patch Set 19: (1 comment) File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/66992/comment/c2e073f9_148f3199 PS14, Line 439: /* GPP_B11 : [] ==> EN_FP_PWR */ : PAD_CFG_GPO(GPP_B11, 0, DEEP), > To be complete, I'd like us to measure (with oscilloscope) and record the timings so we can referenc […] Will follow up on that comment and post the measurement later. -- To view, visit https://review.coreboot.org/c/coreboot/+/66992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Gerrit-Change-Number: 66992 Gerrit-PatchSet: 19 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 22:28:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Comment-In-Reply-To: Eran Mitrani <mitrani(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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