coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: drivers/spi: Add support for Macronix SPI ROM MX77U25650F
by Julius Werner (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: ritul guru. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69381 ) Change subject: drivers/spi: Add support for Macronix SPI ROM MX77U25650F ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74 Gerrit-Change-Number: 69381 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 00:30:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cbfstool: Fix possible memory leak
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69220 ) Change subject: cbfstool: Fix possible memory leak ...................................................................... cbfstool: Fix possible memory leak Handle the possible memory leak scenario. Foundby=klocwork BUG=NONE TEST=Boot to OS on Nivviks Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e Signed-off-by: Shaik Shahina <shahina.shaik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69220 Reviewed-by: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M util/cbfstool/cbfstool.c M util/cbfstool/common.c 2 files changed, 28 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Shahina Shaik: Looks good to me, but someone else must approve diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 04b91e5..d26c418 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -770,8 +770,8 @@ */ if (param.topswap_size) { if (update_master_header_loc_topswap(&image, h_loc, - header_offset)) - return 1; + header_offset)) + goto done; } ret = maybe_update_metadata_hash(&image); diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 8ae9120..7154bc9 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -34,8 +34,13 @@ if (!buffer->data) { fprintf(stderr, "buffer_create: Insufficient memory (0x%zx).\n", size); + if (buffer->name) { + free(buffer->name); + buffer->name = NULL; + } + return -1; } - return (buffer->data == NULL); + return 0; } int buffer_from_file_aligned_size(struct buffer *buffer, const char *filename, -- To view, visit https://review.coreboot.org/c/coreboot/+/69220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e Gerrit-Change-Number: 69220 Gerrit-PatchSet: 7 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: vboot: Introduce handy vboot reboot functions
by 9elements QA (Code Review) 09 Nov '22

09 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69208 ) Change subject: vboot: Introduce handy vboot reboot functions ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134908 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134907 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134906 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134905 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134904 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134903 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134902 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134901 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134900 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134899 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134898 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134897 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134896 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134895 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134894 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134893 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5 Gerrit-Change-Number: 69208 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 00:26:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/ipmi/ocp: add functions to get board configuration
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68779 ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/ipmi/ocp: add functions to get board configuration ...................................................................... drivers/ipmi/ocp: add functions to get board configuration These functions are added for ramstage: * add IPMI OEM command to get board configuration. * add function to get blade index in the sled. Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68779 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h M src/drivers/ipmi/ocp/ipmi_sel.c 3 files changed, 63 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Christian Walter: Looks good to me, approved diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc index fc56364..2b492e1 100644 --- a/src/drivers/ipmi/ocp/Makefile.inc +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c +ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c ipmi_sel.c ifeq ($(CONFIG_IPMI_OCP),y) romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ocp_romstage.c smm-$(CONFIG_IPMI_BMC_SEL) += ipmi_sel.c diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h index c479e52..571eafc 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.h +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -11,6 +11,7 @@ #define IPMI_BMC_SET_POST_START 0x73 #define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 #define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 +#define IPMI_OEM_GET_BOARD_ID 0x37 #define CMOS_BIT (1 << 1) #define VALID_BIT (1 << 7) @@ -101,6 +102,13 @@ uint8_t rsvd2; } __packed; +struct ipmi_config_rsp { + uint8_t board_sku_id; + uint8_t board_rev_id; + uint8_t slot_id; + uint8_t slot_config_id; +} __packed; + #define SEL_RECORD_ID 0x01 #define SEL_PCIE_DEV_ERR 0x20 #define SEL_PCIE_IIO_ERR 0x23 @@ -167,4 +175,7 @@ uint8_t prmry_id); void ipmi_send_sel_pcie_dev_fail(uint16_t sts_reg, uint16_t src_id, enum fail_type code); void ipmi_send_sel_iio_err(uint8_t iio_stack_num, uint8_t err_id); + +enum cb_err ipmi_get_board_config(const int port, struct ipmi_config_rsp *config); +uint8_t get_blade_id(void); #endif diff --git a/src/drivers/ipmi/ocp/ipmi_sel.c b/src/drivers/ipmi/ocp/ipmi_sel.c index 55c0c3e..b10755f 100644 --- a/src/drivers/ipmi/ocp/ipmi_sel.c +++ b/src/drivers/ipmi/ocp/ipmi_sel.c @@ -79,3 +79,35 @@ printk(BIOS_DEBUG, "\terror_code = %x, src_id = %x\n", ubslp.type, ubslp.failure_details2); } + +enum cb_err ipmi_get_board_config(const int port, struct ipmi_config_rsp *config) +{ + int ret; + struct ipmi_oem_rsp { + struct ipmi_rsp resp; + struct ipmi_config_rsp data; + } __packed; + + struct ipmi_oem_rsp rsp; + + ret = ipmi_message(port, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID, NULL, 0, + (unsigned char *)&rsp, sizeof(rsp)); + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + *config = rsp.data; + return CB_SUCCESS; +} + +__weak uint8_t get_blade_id(void) +{ + struct ipmi_config_rsp rsp = {.slot_id = UINT8_MAX}; + + if (CONFIG(IPMI_KCS) && CONFIG_BMC_KCS_BASE) { + if (ipmi_get_board_config(CONFIG_BMC_KCS_BASE, &rsp) != CB_SUCCESS) + return UINT8_MAX; + } + return rsp.slot_id; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ec7ba68d580c13e368e7d656dba47ea043d33e Gerrit-Change-Number: 68779 Gerrit-PatchSet: 9 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER
by Caveh Jalali (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Tarun Tuli, Jason Nien, Caveh Jalali, Kapil Porwal, Nick Vaccaro, Martin Roth, Boris Mittelberg. Hello Tarun Tuli, Subrata Banik, Jason Nien, Kapil Porwal, Nick Vaccaro, Martin Roth, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69374 to look at the new patch set (#4). Change subject: ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER ...................................................................... ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all references. BUG=b:216485035,b:258126464 BRANCH=none TEST=none Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/auron/ec.h M src/mainboard/google/brya/variants/baseboard/brask/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/nissa/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/skolas/include/baseboard/ec.h M src/mainboard/google/brya/variants/redrix4es/include/variant/ec.h M src/mainboard/google/cyan/ec.h M src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/dedede/variants/shotzo/include/variant/ec.h M src/mainboard/google/glados/ec.h M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/link/ec.h M src/mainboard/google/octopus/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/rambi/ec.h M src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/reef/variants/sand/include/variant/ec.h M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/ec.h M src/mainboard/google/slippy/ec.h M src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/kblrvp/ec.h M src/mainboard/intel/kunimitsu/ec.h M src/mainboard/intel/strago/ec.h 23 files changed, 19 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/69374/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Gerrit-Change-Number: 69374 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: drivers/ipmi/ocp: add PCIe SEL support
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68758 ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/ipmi/ocp: add PCIe SEL support ...................................................................... drivers/ipmi/ocp: add PCIe SEL support Add Kconfig SOC_RAS_BMS_SEL and corresponding support for generating PCIe error SEL records and sending them to BMC. Add PCIe error definitions. This is needed for SMM, so build the ipmi kcs driver in SMM. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68758 Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ocp/Kconfig M src/drivers/ipmi/ocp/Makefile.inc M src/drivers/ipmi/ocp/ipmi_ocp.h A src/drivers/ipmi/ocp/ipmi_sel.c 5 files changed, 251 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Christian Walter: Looks good to me, approved diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 85f3dde..28ff78c 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -8,3 +8,4 @@ romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops_premem.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c +smm-$(CONFIG_SOC_RAS_BMC_SEL) += ipmi_kcs.c diff --git a/src/drivers/ipmi/ocp/Kconfig b/src/drivers/ipmi/ocp/Kconfig index 7899e69..c048e20 100644 --- a/src/drivers/ipmi/ocp/Kconfig +++ b/src/drivers/ipmi/ocp/Kconfig @@ -3,3 +3,17 @@ default n help This implements OCP specific IPMI command + +config IPMI_BMC_SEL + bool + depends on IPMI_OCP + default n + help + This implements OCP specific command to generate/send SEL record + +config RAS_SEL_VENDOR_ID + hex + depends on IPMI_BMC_SEL + default 0xff + help + This option specifies a vendor ID for BMC SEL messages diff --git a/src/drivers/ipmi/ocp/Makefile.inc b/src/drivers/ipmi/ocp/Makefile.inc index c77ee4a..fc56364 100644 --- a/src/drivers/ipmi/ocp/Makefile.inc +++ b/src/drivers/ipmi/ocp/Makefile.inc @@ -1,4 +1,5 @@ ramstage-$(CONFIG_IPMI_OCP) += ipmi_ocp.c ifeq ($(CONFIG_IPMI_OCP),y) romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ocp_romstage.c +smm-$(CONFIG_IPMI_BMC_SEL) += ipmi_sel.c endif diff --git a/src/drivers/ipmi/ocp/ipmi_ocp.h b/src/drivers/ipmi/ocp/ipmi_ocp.h index bd15aa3..c479e52 100644 --- a/src/drivers/ipmi/ocp/ipmi_ocp.h +++ b/src/drivers/ipmi/ocp/ipmi_ocp.h @@ -4,6 +4,7 @@ #define __IPMI_OCP_H #include <commonlib/bsd/cb_err.h> +#include <device/pci_type.h> #define IPMI_NETFN_OEM 0x30 #define IPMI_OEM_SET_PPIN 0x77 @@ -33,6 +34,137 @@ uint8_t boot_dev4; } __packed; +struct pci_dev_fn { + u32 func:15; + u32 dev:5; + u32 bus:12; +}; + +struct ipmi_pci_dev_fn { + uint16_t func:3; + uint16_t dev:5; + uint16_t bus:8; +}; + +struct ipmi_sel_pcie_dev_err { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + uint16_t aux_loc; + struct ipmi_pci_dev_fn bdf; + uint16_t primary_err_count; + uint8_t secondary_id; + uint8_t primary_id; +} __packed; + +struct iio_port_location { + uint8_t socket:4; + uint8_t sled:2; + uint8_t rsvd:2; +}; + +struct ipmi_sel_iio_err { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + struct iio_port_location loc; + uint8_t iio_stack_num; + uint8_t rsvd0; + uint8_t rsvd1; + uint8_t iio_err_id; + uint8_t rsvd2; + uint8_t rsvd3; + uint8_t rsvd4; +} __packed; + +enum fail_type { + PCIE_DPC_EVNT = 0, + PCIE_LER_EVNT = 1, + PCIE_LRTRN_REC = 2, + PCIE_CRC_RETRY = 3, + PCIE_CRPT_DATA_CONTMT = 4, + PCIE_ECRC_EVNT = 5, +}; + +struct ipmi_sel_pcie_dev_fail { + uint16_t record_id; + uint8_t record_type; + uint8_t general_info; + uint32_t timestamp; + enum fail_type type; + uint8_t rsvd0; + uint16_t failure_details1; /* if DPC, DPC sts reg of root port */ + uint16_t failure_details2; /* if DPC, source ID of root port */ + uint8_t rsvd1; + uint8_t rsvd2; +} __packed; + +#define SEL_RECORD_ID 0x01 +#define SEL_PCIE_DEV_ERR 0x20 +#define SEL_PCIE_IIO_ERR 0x23 +#define SEL_PCIE_DEV_FAIL_ID 0x29 + +/* PCIE Unified Messages */ + +/* PCIE CE */ +#define RECEIVER_ERROR 0x00 +#define BAD_TLP 0x01 +#define BAD_DLLP 0x02 +#define REPLAY_TIME_OUT 0x03 +#define REPLAY_NUMBER_ROLLOVER 0x04 +#define ADVISORY_NONFATAL_ERROR_STATUS 0x05 +#define CORRECTED_INTERNAL_ERROR_STATUS 0x06 +#define HEADER_LOG_OVERFLOW_STATUS 0x07 + +/* PCIE UCE */ +#define PCI_EXPRESS_DATA_LINK_PROTOCOL_ERROR 0x20 +#define SURPRISE_DOWN_ERROR 0x21 +#define RECEIVED_PCI_EXPRESS_POISONED_TLP 0x22 +#define PCI_EXPRESS_FLOW_CONTROL_PROTOCOL_ERROR 0x23 +#define COMPLETION_TIMEOUT_ON_NP_TRANSACTIONS_OUTSTANDING_ON_PCI_EXPRESS_DMI 0x24 +#define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_TO_BE_COMPLETER_ABORTED 0x25 +#define RECEIVED_PCI_EXPRESS_UNEXPECTED_COMPLETION 0x26 +#define PCI_EXPRESS_RECEIVER_OVERFLOW 0x27 +#define PCI_EXPRESS_MALFORMED_TLP 0x28 +#define ECRC_ERROR_STATUS 0x29 +#define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_UNSUPPORTED 0x2A +#define ACS_VIOLATION 0x2B +#define UNCORRECTABLE_INTERNAL_ERROR_STATUS 0x2C +#define MC_BLOCKED_TLP 0x2D +#define ATOMICOP_EGRESS_BLOCKED_STATUS 0x2E +#define TLP_PREFIX_BLOCKED_ERROR_STATUS 0x2F +#define POISONED_TLP_EGRESS_BLOCKED 0x30 + +/* Root error status (from PCIE spec) */ +#define RECEIVED_ERR_COR_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x50 +#define RECEIVED_ERR_NONFATAL_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x51 +#define RECEIVED_ERR_FATAL_MESSAGE_FROM_DOWNSTREAM_DEVICE 0x52 + +/* DPC Trigger Reason */ +#define DPC_WAS_TRIGGERED_DUE_TO_AN_UNMASKED_UNCORRECTABLE_ERROR 0x53 +#define DPC_WAS_TRIGGERED_DUE_TO_RECEIVING_AN_ERR_NONFATAL 0x54 +#define DPC_WAS_TRIGGERED_DUE_TO_RECEIVING_AN_ERR_FATAL 0x55 +#define DPC_WAS_TRIGGERED_DUE_TO_RP_PIO_ERROR 0x56 +#define DPC_WAS_TRIGGERED_DUE_TO_THE_DPC_SOFTWARE_TRIGGER_BIT 0x57 + +#define OUTBOUND_SWITCH_FIFO_DATA_PARITY_ERROR_DETECTED 0x80 +#define SENT_A_PCI_EXPRESS_COMPLETER_ABORT 0x81 +#define SENT_A_PCI_EXPRESS_UNSUPPORTED_REQUEST 0x82 +#define RECEIVED_COMPLETER_ABORT 0x83 +#define RECEIVED_UNSUPPORTED_REQUEST_COMPLETION_STATUS_FROM_DOWNSTREAM_DEVICE 0x84 +#define RECEIVED_MSI_WRITES_GREATER_THAN_A_DWORD 0x85 +#define OUTBOUND_POISONED_DATA 0x86 +#define PERR_NON_AER 0xA0 +#define SERR_NON_AER 0xA1 + enum cb_err ipmi_set_post_start(const int port); enum cb_err ipmi_set_cmos_clear(void); + +void ipmi_send_to_bmc(unsigned char *data, size_t size); +void ipmi_send_sel_pcie_dev_err(pci_devfn_t bdf, uint16_t prmry_cnt, uint8_t sec_id, + uint8_t prmry_id); +void ipmi_send_sel_pcie_dev_fail(uint16_t sts_reg, uint16_t src_id, enum fail_type code); +void ipmi_send_sel_iio_err(uint8_t iio_stack_num, uint8_t err_id); #endif diff --git a/src/drivers/ipmi/ocp/ipmi_sel.c b/src/drivers/ipmi/ocp/ipmi_sel.c new file mode 100644 index 0000000..55c0c3e --- /dev/null +++ b/src/drivers/ipmi/ocp/ipmi_sel.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <string.h> + +#include "ipmi_ocp.h" + +static int ipmi_add_sel_entry(int port, unsigned char *data, int size) +{ + return ipmi_message(port, IPMI_NETFN_STORAGE, 0, IPMI_ADD_SEL_ENTRY, data, size, + NULL, 0); +} + +void ipmi_send_to_bmc(unsigned char *data, size_t size) +{ + if (CONFIG(IPMI_KCS)) { + _Static_assert(CONFIG_BMC_KCS_BASE != 0, + "\tBMC_ERROR: Unable to send record: Port #:0\n"); + + ipmi_add_sel_entry(CONFIG_BMC_KCS_BASE, data, size); + } +} + +void ipmi_send_sel_iio_err(uint8_t iio_stack_num, uint8_t err_id) +{ + struct ipmi_sel_iio_err ubslp = { + .record_id = SEL_RECORD_ID, + .record_type = CONFIG_RAS_SEL_VENDOR_ID, + .general_info = SEL_PCIE_IIO_ERR, + .iio_stack_num = iio_stack_num, + .iio_err_id = err_id, + }; + + ipmi_send_to_bmc((unsigned char *)&ubslp, sizeof(ubslp)); + printk(BIOS_DEBUG, "\tsending PCIE IIO device error record to BMC\n"); + printk(BIOS_DEBUG, "\tstack # = %x\n", ubslp.iio_stack_num); +} + +void ipmi_send_sel_pcie_dev_err(pci_devfn_t bdf, uint16_t prmry_cnt, uint8_t sec_id, + uint8_t prmry_id) +{ + struct pci_dev_fn *inbdf = (struct pci_dev_fn *)&bdf; + struct ipmi_sel_pcie_dev_err ubslp = { + .record_id = SEL_RECORD_ID, + .record_type = CONFIG_RAS_SEL_VENDOR_ID, + .general_info = SEL_PCIE_DEV_ERR, + .timestamp = 0, /* BMC will apply timestamp */ + .aux_loc = 0, + .bdf.bus = inbdf->bus, + .bdf.dev = inbdf->dev, + .bdf.func = inbdf->func >> 12, + .primary_err_count = prmry_cnt, + .primary_id = prmry_id, + .secondary_id = sec_id, + }; + + ipmi_send_to_bmc((unsigned char *)&ubslp, sizeof(ubslp)); + printk(BIOS_DEBUG, "\tsending PCIE device error record to BMC\n"); + printk(BIOS_DEBUG, "\tbdf = %x:%x:%x\n", ubslp.bdf.bus, ubslp.bdf.dev, ubslp.bdf.func); + printk(BIOS_DEBUG, "\tubslp.primary_id = %x\n", ubslp.primary_id); + printk(BIOS_DEBUG, "\tsecondary_id = %x\n", ubslp.secondary_id); +} + +void ipmi_send_sel_pcie_dev_fail(uint16_t sts_reg, uint16_t src_id, enum fail_type code) +{ + struct ipmi_sel_pcie_dev_fail ubslp = { + .record_id = SEL_RECORD_ID, + .record_type = CONFIG_RAS_SEL_VENDOR_ID, + .general_info = SEL_PCIE_DEV_FAIL_ID, + .timestamp = 0, /* BMC will apply timestamp */ + .type = code, + .failure_details1 = sts_reg, + .failure_details2 = src_id, + }; + + ipmi_send_to_bmc((unsigned char *)&ubslp, sizeof(ubslp)); + printk(BIOS_DEBUG, "\tsending PCI device FAILURE record to BMC\n"); + printk(BIOS_DEBUG, "\terror_code = %x, src_id = %x\n", ubslp.type, + ubslp.failure_details2); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Gerrit-Change-Number: 68758 Gerrit-PatchSet: 10 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/clevo/l140cu: drop System76 EC
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michal Zygowski, Michael Niewöhner. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59816 ) Change subject: mb/clevo/l140cu: drop System76 EC ...................................................................... Patch Set 15: -Code-Review (1 comment) Patchset: PS15: Sorry, my mistake - I thought the system76 board was relying on this, but that doesn't seem to be the case. Carry on. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/59816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5 Gerrit-Change-Number: 59816 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 00:06:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/clevo/l140cu: drop System76 EC
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Felix Singer, Michał Żygowski, Michal Zygowski, Michael Niewöhner. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59816 ) Change subject: mb/clevo/l140cu: drop System76 EC ...................................................................... Patch Set 15: Code-Review-2 (1 comment) Patchset: PS15: Let's not do this without verifying with the s76 Team. They're not even added as reviewers. -- To view, visit https://review.coreboot.org/c/coreboot/+/59816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06abbde238be6d25842472a6a82159413ab52ef5 Gerrit-Change-Number: 59816 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 00:00:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
by Reka Norman (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Tarun Tuli, Michał Żygowski, Kangheui Won, Paul Menzel, Rizwan Qureshi, Sridhar Siricilla. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69324 ) Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69324/comment/e4368829_8db1167a PS1, Line 22: On an anahera which has gone through EOM: > Add a blank above? Done https://review.coreboot.org/c/coreboot/+/69324/comment/875292ef_9c07dc74 PS1, Line 24: > Before the patch, firmware used to check only 2 conditions (#1 and #2 as mentioned in the commit mes […] I think Paul meant what was the output before the patch. Added. File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/69324/comment/91e16c96_d243649f PS1, Line 141: hfsts1.fields.mfg_mode > What I am trying to say is that when somebody reflashes the descriptor externally or do not decide t […] I see your point that it's a bit arbitrary exactly which conditions the Manufacturing Mode log should represent. I think it makes most sense to follow the definition in Intel documentation, which for ADL clearly says a device should be considered in production mode only if all three criteria are met, and customers should use the individual indicators to determine exactly which steps have been done. In the latest patchset I've added logs for each of individual criteria to make it easier to tell why Manufacturing Mode is set or not. -- To view, visit https://review.coreboot.org/c/coreboot/+/69324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Gerrit-Change-Number: 69324 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 00:00:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
by Reka Norman (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Tarun Tuli, Kangheui Won, Paul Menzel, Reka Norman, Rizwan Qureshi, Sridhar Siricilla. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kangheui Won, Rizwan Qureshi, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69324 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, 1 and 2 are already checked. Add a check for 3 as well. Also add logs for each individual criteria so it's easy to tell why the overall Manufacturing Mode is set or not. BUG=b:255462682 TEST=On a nivviks which has not gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO After: [DEBUG] ME: Manufacturing Mode : YES [DEBUG] ME: SPI Protection Mode Enabled : NO [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Manufacturing Vars Locked : NO On an anahera which has gone through EOM: Before: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES After: [DEBUG] ME: Manufacturing Mode : NO [DEBUG] ME: SPI Protection Mode Enabled : YES [DEBUG] ME: FPFs Committed : YES [DEBUG] ME: Manufacturing Vars Locked : YES Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/soc/intel/alderlake/me.c 1 file changed, 54 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/69324/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Gerrit-Change-Number: 69324 Gerrit-PatchSet: 2 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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