coreboot-gerrit November 2022

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[M] Change in coreboot[master]: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
by Mario Scheithauer (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69387 to look at the new patch set (#5). Change subject: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver ...................................................................... mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed. For LED[2] we do not need to set anything, since this is used as INTn. The correct setting for INTn is brought out LED[2] will be done in following up patch. This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link LED[2] - no setting need because INTn is brought out LED[2] TEST=Try different register values to verify LED feature. Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 57 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69387/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Gerrit-Change-Number: 69387 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: /: Remove "ERROR: "/"WARNING: " prefixes from log messages
by Elyes Haouas (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69405 to look at the new patch set (#3). Change subject: /: Remove "ERROR: "/"WARNING: " prefixes from log messages ...................................................................... /: Remove "ERROR: "/"WARNING: " prefixes from log messages It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c M src/device/pci_device.c M src/soc/amd/glinda/i2c.c M src/soc/amd/glinda/psp_verstage/chipset.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/mendocino/i2c.c M src/soc/amd/mendocino/psp_verstage/chipset.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/morgana/i2c.c M src/soc/amd/morgana/psp_verstage/chipset.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/morgana/smihandler.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_ctrl.c 16 files changed, 45 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69405/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Gerrit-Change-Number: 69405 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: /: Remove "ERROR: "/"WARNING: " prefixes from log messages
by Elyes Haouas (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69405 to look at the new patch set (#2). Change subject: /: Remove "ERROR: "/"WARNING: " prefixes from log messages ...................................................................... /: Remove "ERROR: "/"WARNING: " prefixes from log messages It is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c M src/device/pci_device.c M src/soc/amd/glinda/i2c.c M src/soc/amd/glinda/psp_verstage/chipset.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/mendocino/i2c.c M src/soc/amd/mendocino/psp_verstage/chipset.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/morgana/i2c.c M src/soc/amd/morgana/psp_verstage/chipset.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/morgana/smihandler.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_ctrl.c 16 files changed, 45 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69405/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Gerrit-Change-Number: 69405 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: /: Remove "ERROR: "/"Error: " prefixes from log messages
by Elyes Haouas (Code Review) 09 Nov '22

09 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69405 ) Change subject: /: Remove "ERROR: "/"Error: " prefixes from log messages ...................................................................... /: Remove "ERROR: "/"Error: " prefixes from log messages It is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c M src/device/pci_device.c M src/soc/amd/glinda/i2c.c M src/soc/amd/glinda/psp_verstage/chipset.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/mendocino/i2c.c M src/soc/amd/mendocino/psp_verstage/chipset.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/morgana/i2c.c M src/soc/amd/morgana/psp_verstage/chipset.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/morgana/smihandler.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_ctrl.c 16 files changed, 45 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69405/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 8dabad5..55295ca 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -259,10 +259,10 @@ write_le32(&pe_base[aoff], val + delta); break; case EFI_IMAGE_REL_BASED_DIR64: - printk(BIOS_ERR, "Error: Unsupported DIR64\n"); + printk(BIOS_ERR, "Unsupported DIR64\n"); break; default: - printk(BIOS_ERR, "Error: Unsupported relocation type %d\n", + printk(BIOS_ERR, "Unsupported relocation type %d\n", rtype); return -1; } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 70af9c5..16c31ea 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -408,7 +408,7 @@ int max_requested_bits = __fls64(size_mask); if (max_requested_bits > CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS) { - printk(BIOS_WARNING, "WARNING: Device %s requests a BAR with" + printk(BIOS_WARNING, "Device %s requests a BAR with" " %u bits of address space, which coreboot is not" " configured to hand out, truncating to %u bits\n", dev_path(dev), max_requested_bits, @@ -417,7 +417,7 @@ } if (!(res->flags & IORESOURCE_PCI64) && max_requested_bits > 32) { - printk(BIOS_ERR, "ERROR: Resizable BAR requested" + printk(BIOS_ERR, "Resizable BAR requested" " above 32 bits, but PCI function reported a" " 32-bit BAR."); return; diff --git a/src/soc/amd/glinda/i2c.c b/src/soc/amd/glinda/i2c.c index 97b982b..bd3d4dc 100644 --- a/src/soc/amd/glinda/i2c.c +++ b/src/soc/amd/glinda/i2c.c @@ -34,7 +34,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } diff --git a/src/soc/amd/glinda/psp_verstage/chipset.c b/src/soc/amd/glinda/psp_verstage/chipset.c index 2366909..b266fc2 100644 --- a/src/soc/amd/glinda/psp_verstage/chipset.c +++ b/src/soc/amd/glinda/psp_verstage/chipset.c @@ -24,7 +24,7 @@ uint32_t len; if (!spi_ptr) { - printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); /* * If we don't supply hash table, the PSP will refuse to boot. * So returning here is safe to do. @@ -36,7 +36,7 @@ if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; @@ -44,7 +44,7 @@ if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index ef6c630..2a4a547 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -158,7 +158,7 @@ mmconf_resource(dev, idx++); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -180,7 +180,7 @@ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "Failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/glinda/smihandler.c b/src/soc/amd/glinda/smihandler.c index 95d12bf..9cc34b5 100644 --- a/src/soc/amd/glinda/smihandler.c +++ b/src/soc/amd/glinda/smihandler.c @@ -100,7 +100,7 @@ psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c index 75efe0c..92e46b9 100644 --- a/src/soc/amd/mendocino/i2c.c +++ b/src/soc/amd/mendocino/i2c.c @@ -32,7 +32,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } diff --git a/src/soc/amd/mendocino/psp_verstage/chipset.c b/src/soc/amd/mendocino/psp_verstage/chipset.c index b896279..fe79979 100644 --- a/src/soc/amd/mendocino/psp_verstage/chipset.c +++ b/src/soc/amd/mendocino/psp_verstage/chipset.c @@ -24,7 +24,7 @@ uint32_t len; if (!spi_ptr) { - printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); /* * If we don't supply hash table, the PSP will refuse to boot. * So returning here is safe to do. @@ -36,7 +36,7 @@ if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; @@ -44,7 +44,7 @@ if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6768613..7feb7f7 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -158,7 +158,7 @@ mmconf_resource(dev, idx++); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -180,7 +180,7 @@ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "Failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/mendocino/smihandler.c b/src/soc/amd/mendocino/smihandler.c index c05f3ee..8e32b5d 100644 --- a/src/soc/amd/mendocino/smihandler.c +++ b/src/soc/amd/mendocino/smihandler.c @@ -100,7 +100,7 @@ psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/amd/morgana/i2c.c b/src/soc/amd/morgana/i2c.c index 92dd00d..0e416cf 100644 --- a/src/soc/amd/morgana/i2c.c +++ b/src/soc/amd/morgana/i2c.c @@ -32,7 +32,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } diff --git a/src/soc/amd/morgana/psp_verstage/chipset.c b/src/soc/amd/morgana/psp_verstage/chipset.c index 539ddb4..2f5fb44 100644 --- a/src/soc/amd/morgana/psp_verstage/chipset.c +++ b/src/soc/amd/morgana/psp_verstage/chipset.c @@ -24,7 +24,7 @@ uint32_t len; if (!spi_ptr) { - printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); /* * If we don't supply hash table, the PSP will refuse to boot. * So returning here is safe to do. @@ -36,7 +36,7 @@ if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; @@ -44,7 +44,7 @@ if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; diff --git a/src/soc/amd/morgana/root_complex.c b/src/soc/amd/morgana/root_complex.c index 88bcca7..1a4f0bd 100644 --- a/src/soc/amd/morgana/root_complex.c +++ b/src/soc/amd/morgana/root_complex.c @@ -158,7 +158,7 @@ mmconf_resource(dev, idx++); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -180,7 +180,7 @@ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "Failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/morgana/smihandler.c b/src/soc/amd/morgana/smihandler.c index a1eabed..d04f9a3 100644 --- a/src/soc/amd/morgana/smihandler.c +++ b/src/soc/amd/morgana/smihandler.c @@ -100,7 +100,7 @@ psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c index 4e5f7da..2d2821b 100644 --- a/src/soc/qualcomm/sc7280/display/edp_aux.c +++ b/src/soc/qualcomm/sc7280/display/edp_aux.c @@ -32,13 +32,13 @@ u32 intr_status = 0; if (!wait_ms(100, read32(&edp_auxclk->status) & EDP_AUX_INTERRUPT)) { - printk(BIOS_ERR, "ERROR: AUX SEND not acknowledged\n"); + printk(BIOS_ERR, "AUX SEND not acknowledged\n"); return; } intr_status = read32(&edp_auxclk->status); if (!(intr_status & AUX_INTR_I2C_DONE)) { - printk(BIOS_ERR, "ERROR: AUX command failed, status = %#x\n", intr_status); + printk(BIOS_ERR, "AUX command failed, status = %#x\n", intr_status); return; } @@ -176,7 +176,7 @@ err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_READ, edid, EDID_LENGTH); if (err < EDID_LENGTH) { - printk(BIOS_ERR, "ERROR: Failed to read EDID. :%d\n", err); + printk(BIOS_ERR, "Failed to read EDID. :%d\n", err); return err; } @@ -196,7 +196,7 @@ } if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { - printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n"); + printk(BIOS_ERR, "Failed to decode EDID.\n"); return CB_ERR; } diff --git a/src/soc/qualcomm/sc7280/display/edp_ctrl.c b/src/soc/qualcomm/sc7280/display/edp_ctrl.c index e9254cc..1455cac 100644 --- a/src/soc/qualcomm/sc7280/display/edp_ctrl.c +++ b/src/soc/qualcomm/sc7280/display/edp_ctrl.c @@ -1375,7 +1375,7 @@ if (dpcd[DP_DPCD_REV] >= 0x11) { ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_READ, &value, 1); if (ret < 0) { - printk(BIOS_ERR, "ERROR: edp native read failure\n"); + printk(BIOS_ERR, "edp native read failure\n"); return -1; } @@ -1384,7 +1384,7 @@ ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_WRITE, &value, 1); if (ret < 0) { - printk(BIOS_ERR, "ERROR: edp native read failure\n"); + printk(BIOS_ERR, "edp native read failure\n"); return -1; } @@ -1401,7 +1401,7 @@ /* Start link training */ ret = edp_ctrl_training(ctrl, edid, dpcd); if (ret != EDP_TRAIN_SUCCESS) { - printk(BIOS_ERR, "ERROR: edp training failure\n"); + printk(BIOS_ERR, "edp training failure\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Gerrit-Change-Number: 69405 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Jakub Czapiga (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Philipp Hug, Matt DeVillier, Angel Pons, Andrey Petrov, ron minnich, Elyes Haouas, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/soc/nvidia/tegra124/cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/ff683c31_1e20a342 PS7, Line 9: << 20UL; `* MiB` -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 13:54:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by Mario Scheithauer (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 4: (2 comments) File src/drivers/phy/m88e1512/m88e1512.h: https://review.coreboot.org/c/coreboot/+/69386/comment/9f52f5fd_582dca36 PS3, Line 7: PHY_MDIO_PAGE_ANY_ADR_RE > This name is a bit misleading. In the linked datasheet this register is called 'Page Address'. […] Ack. It looks better and makes it clearer. You are also right about the defines for the pages. File src/drivers/phy/m88e1512/m88e1512.c: https://review.coreboot.org/c/coreboot/+/69386/comment/02856151_aa3655ac PS3, Line 22: ... > Just one '.' should be suitable here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 13:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Raul Rangel, Jeff Daly, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Angel Pons, Arthur Heymans, Andrey Petrov, Jason Glenesk, Johnny Lin, Christian Walter, Vanessa Eusebio, Fred Reitberger, Tim Chu, Felix Held. Hello Jeff Daly, Raul Rangel, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Angel Pons, Arthur Heymans, Andrey Petrov, Jason Glenesk, Johnny Lin, Christian Walter, Vanessa Eusebio, Fred Reitberger, Felix Held, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69163 to look at the new patch set (#5). Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/mrc_cache/mrc_cache.c M src/drivers/smmstore/ramstage.c M src/include/cbmem.h M src/include/imd.h M src/lib/bmp_logo.c M src/lib/cbfs.c M src/lib/cbmem_stage_cache.c M src/lib/ext_stage_cache.c M src/lib/fmap.c M src/lib/imd.c M src/lib/imd_cbmem.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/uncore.c M tests/lib/imd_cbmem-test.c 47 files changed, 102 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69163/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Mario Scheithauer (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Angel Pons, Lean Sheng Tan, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/elkhartlake/mdio.c: https://review.coreboot.org/c/coreboot/+/69383/comment/0952dda1_ce92adfe PS3, Line 3: #define __SIMPLE_DEVICE__ > Do we need this even if this file is compiled just for the ramstage? Ack File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/d867f22e_5b50b865 PS3, Line 41: %s Cannot find MDIO bus operations > What about 'MDIO bus operations not available for %s. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 13:46:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by build bot (Jenkins) (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Mario Scheithauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 4: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163104): https://review.coreboot.org/c/coreboot/+/69386/comment/f5f68685_c8c04cf3 PS4, Line 14: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/… Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 13:45:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by Mario Scheithauer (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Mario Scheithauer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69386 to look at the new patch set (#4). Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... drivers/phy/m88e1512: Provide functionality to customize LED status For Marvel PHY it could be necessary to customize the shown LED status at the connector. The LED status can be changed via PHY Function Control Register on page 3. Link to the Marvell PHY 88E1512 datasheet: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/… Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- A src/drivers/phy/m88e1512/chip.h M src/drivers/phy/m88e1512/m88e1512.c A src/drivers/phy/m88e1512/m88e1512.h 3 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/69386/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022