coreboot-gerrit November 2022

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[S] Change in coreboot[master]: cpu/x86/smm/module_loader: Fix ASEG loading
by Felix Held (Code Review) 09 Nov '22

09 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69233 ) Change subject: cpu/x86/smm/module_loader: Fix ASEG loading ...................................................................... cpu/x86/smm/module_loader: Fix ASEG loading This code was never tested with SSE enabled. Now qemu enables it and FX_SAVE encroaches on the save states. Without SSE enabled the handler just happened to be aligned downwards enough to have the save states fit. With SSE enabled that's not the case. The proper fix is to give the code setting up stubs the right base address, which is the same as for the TSEG codepath. Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69233 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 27 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 71d49ab..6f334a2 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -409,6 +409,11 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params) { + if (CONFIG(SMM_ASEG) && (smram_base != SMM_BASE || smram_size != SMM_CODE_SEGMENT_SIZE)) { + printk(BIOS_ERR, "SMM base & size are 0x%lx, 0x%zx, but must be 0x%x, 0x%x\n", + smram_base, smram_size, SMM_BASE, SMM_CODE_SEGMENT_SIZE); + return -1; + } /* * Place in .bss to reduce stack usage. * TODO: once CPU_INFO_V2 is used everywhere, use smaller stack for APs and move @@ -457,18 +462,7 @@ if (append_and_check_region(smram, handler, region_list, "HANDLER")) return -1; - uintptr_t stub_segment_base; - - if (CONFIG(SMM_TSEG)) { - stub_segment_base = handler_base - SMM_CODE_SEGMENT_SIZE; - } else if (CONFIG(SMM_ASEG)) { - stub_segment_base = smram_base; - if (smram_base != SMM_BASE || smram_size != SMM_CODE_SEGMENT_SIZE) { - printk(BIOS_ERR, "SMM base & size are 0x%lx, 0x%zx, but must be 0x%x, 0x%x\n", - smram_base, smram_size, SMM_BASE, SMM_CODE_SEGMENT_SIZE); - return -1; - } - } + uintptr_t stub_segment_base = handler_base - SMM_CODE_SEGMENT_SIZE; if (!smm_create_map(stub_segment_base, params->num_concurrent_save_states, params)) { printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/69233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209 Gerrit-Change-Number: 69233 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Raul Rangel, Jeff Daly, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Tim Chu, Felix Held. Hello Jeff Daly, Raul Rangel, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Felix Held, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69163 to look at the new patch set (#7). Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/arch/x86/postcar_loader.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/mrc_cache/mrc_cache.c M src/drivers/smmstore/ramstage.c M src/include/cbmem.h M src/include/imd.h M src/lib/bmp_logo.c M src/lib/cbfs.c M src/lib/cbmem_stage_cache.c M src/lib/ext_stage_cache.c M src/lib/fmap.c M src/lib/imd.c M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/uncore.c M tests/lib/imd_cbmem-test.c 49 files changed, 106 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69163/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
by Matt DeVillier (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Jason Glenesk, Jason Nien, Martin Roth, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69187 ) Change subject: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Gerrit-Change-Number: 69187 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 14:22:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
by Matt DeVillier (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Martin Roth, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69188 ) Change subject: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Gerrit-Change-Number: 69188 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 14:21:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT
by Felix Held (Code Review) 09 Nov '22

09 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69307 ) Change subject: mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT ...................................................................... mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDT Provide timing parameter for SSDT generation to achieve the requested 100 kHz speed with a high accuracy. Test: Measure I2C bus clock, high and low times during I2C access from Linux and confirm they match the specification. Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index d5d1277..3b54f24 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -111,9 +111,21 @@ register "common_soc_config" = "{ .i2c[1] = { .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1e1, + .scl_lcnt = 0x1f4, + .sda_hold = 0x64 + }, }, .i2c[2] = { .speed = I2C_SPEED_STANDARD, + .speed_config[0] = { + .speed = I2C_SPEED_STANDARD, + .scl_hcnt = 0x1df, + .scl_lcnt = 0x1f4, + .sda_hold = 0x64 + }, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/69307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Gerrit-Change-Number: 69307 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS
by Felix Held (Code Review) 09 Nov '22

09 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69306 ) Change subject: mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS ...................................................................... mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OS In Linux, the I2C speed defaults to 400 kHz if there is no device registered in ACPI which requests a different speed. Due to board limitations (layout, bus load), 400 kHz are too fast which results in a timing violation. Therefore, add a dummy I2C device to both used I2C buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus speed in Linux accordingly. Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 34 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4109ec9..d5d1277 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -144,8 +144,21 @@ register "cap_charge" = "CHARGE_OFF" device i2c 0x52 on end # RTC RV3028-C7 end + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end end - device pci 15.2 on end # I2C2 + device pci 15.2 on # I2C2 + # Add dummy I2C device to limit BUS speed to 100 kHz in OS + chip drivers/i2c/generic + register "hid" = ""PRP0001"" + register "speed" = "I2C_SPEED_STANDARD" + device i2c 0x7f on end + end + end device pci 15.3 on end # I2C3 device pci 16.0 hidden end # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Gerrit-Change-Number: 69306 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
by Felix Held (Code Review) 09 Nov '22

09 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69305 ) Change subject: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz ...................................................................... soc/intel/elkhartlake: Correct I2C base clock to 100 MHz According to measurements Elkhart Lake seems to drive the internal I2C controllers with 100 MHz instead of the common 133 MHz. The datasheet itself is quite vague on this definition, just one place mentions that it is 100 MHz (register description for offset 0x94). This patch changes the I2C controller base frequency to 100 MHz. The verification was done by measuring the set up resulting I2C clock for both 100 and 400 kHz. Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 4343e85..8e3dc11 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -151,7 +151,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int - default 133 + default 100 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int -- To view, visit https://review.coreboot.org/c/coreboot/+/69305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Gerrit-Change-Number: 69305 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/i2c/designware: Add 100 MHz controller base clock
by Felix Held (Code Review) 09 Nov '22

09 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69304 ) Change subject: drivers/i2c/designware: Add 100 MHz controller base clock ...................................................................... drivers/i2c/designware: Add 100 MHz controller base clock There are SoCs (for instance Intel Elkhart Lake) that do use 100 MHz as the base clock for I2C controllers. To support them properly add a frequency setting for 100 MHz to the designware I2C controller driver. Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69304 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index ecd9e88..1e3163a 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -196,6 +196,13 @@ struct freq freq; } soc_clocks[] = { { + .clk_speed_mhz = 100, + .freq = { + .ticks = 100, + .ns = 1000, + }, + }, + { .clk_speed_mhz = 120, .freq = { .ticks = 120, -- To view, visit https://review.coreboot.org/c/coreboot/+/69304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769 Gerrit-Change-Number: 69304 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Elyes Haouas (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Raul Rangel, Jeff Daly, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Tim Chu, Felix Held. Hello Jeff Daly, Raul Rangel, Jakub Czapiga, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Felix Held, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69163 to look at the new patch set (#6). Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... cbmem_top: Change the return value to uintptr_t Get rid of a lot of casts. Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/arch/x86/postcar_loader.c M src/cpu/x86/smm/smm_module_loader.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/mrc_cache/mrc_cache.c M src/drivers/smmstore/ramstage.c M src/include/cbmem.h M src/include/imd.h M src/lib/bmp_logo.c M src/lib/cbfs.c M src/lib/cbmem_stage_cache.c M src/lib/ext_stage_cache.c M src/lib/fmap.c M src/lib/imd.c M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/quark/memmap.c M src/soc/intel/quark/northcluster.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/uncore.c M tests/lib/imd_cbmem-test.c 49 files changed, 105 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69163/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Add wifi sar table
by Felix Held (Code Review) 09 Nov '22

09 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68660 ) Change subject: mb/google/nissa/var/craask: Add wifi sar table ...................................................................... mb/google/nissa/var/craask: Add wifi sar table Add wifi sar table for craask/craaskbowl. Use fw_config to separate different project settings. BUG=b:247652032,b:251287099,b:251287101 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68660 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/craask/Makefile.inc M src/mainboard/google/brya/variants/craask/overridetree.cb A src/mainboard/google/brya/variants/craask/variant.c 4 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3c755c6..2102961 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -226,6 +226,7 @@ select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_OSIRIS bool "-> Osiris" diff --git a/src/mainboard/google/brya/variants/craask/Makefile.inc b/src/mainboard/google/brya/variants/craask/Makefile.inc index 8ae0e3b..86ba20d 100644 --- a/src/mainboard/google/brya/variants/craask/Makefile.inc +++ b/src/mainboard/google/brya/variants/craask/Makefile.inc @@ -4,4 +4,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index ebf8c30..fa79d8b 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -20,6 +20,10 @@ field AMP 6 7 option AMP_MX98360A 0 end + field WIFI_SAR_ID 13 15 + option ID_0 0 + option UNUSED 7 + end field CODEC 32 33 option CODEC_ALC5682I_VS 0 option CODEC_NAU8825 1 diff --git a/src/mainboard/google/brya/variants/craask/variant.c b/src/mainboard/google/brya/variants/craask/variant.c new file mode 100644 index 0000000..689a59a --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/variant.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, ID_0))) { + printk(BIOS_INFO, "Use wifi_sar_0.hex.\n"); + return "wifi_sar_0.hex"; + } + + else if (fw_config_probe(FW_CONFIG(WIFI_SAR_ID, UNUSED))) { + printk(BIOS_INFO, "Wi-Fi SAR not used, return NULL!\n"); + } + + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Gerrit-Change-Number: 68660 Gerrit-PatchSet: 10 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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