coreboot-gerrit November 2022

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[S] Change in coreboot[master]: drivers/i2c/designware: Add 100 MHz controller base clock
by 9elements QA (Code Review) 09 Nov '22

09 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69304 ) Change subject: drivers/i2c/designware: Add 100 MHz controller base clock ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135121 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135120 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135119 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135118 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135117 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135116 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135115 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135114 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135113 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135112 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135111 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135110 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135109 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135108 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135107 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135106 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea11c6a41fd3758b771a416251e108cbe722769 Gerrit-Change-Number: 69304 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 16:12:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/chausie/ec.c: Enable WLAN
by Jason Glenesk (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Fred Reitberger, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69319 ) Change subject: mb/amd/chausie/ec.c: Enable WLAN ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Gerrit-Change-Number: 69319 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 16:11:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/chausie/ec.c: Enable WLAN
by Fred Reitberger (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69319 ) Change subject: mb/amd/chausie/ec.c: Enable WLAN ...................................................................... Patch Set 2: (1 comment) File src/mainboard/amd/chausie/ec.c: https://review.coreboot.org/c/coreboot/+/69319/comment/9c1da069_7a47b173 PS1, Line 37: > nit: extra line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Gerrit-Change-Number: 69319 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 16:01:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/chausie/ec.c: Enable WLAN
by Fred Reitberger (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69319 to look at the new patch set (#2). Change subject: mb/amd/chausie/ec.c: Enable WLAN ...................................................................... mb/amd/chausie/ec.c: Enable WLAN Enable WLAN power and deassert the various radio disables. TEST=boot chausie Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a --- M src/mainboard/amd/chausie/ec.c 1 file changed, 41 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/69319/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Gerrit-Change-Number: 69319 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69188 ) Change subject: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl ...................................................................... soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl Instead of including pci_int_defs.asl in each board's DSDT, include it in the common soc.asl. This moves the PRQM OperationRegion and the PRQI IndexField defined in pci_int_defs.asl into the \_SB scope, but those are defined inside the \_SB scope both in the Picasso reference code and for the AMD SoCs from Cezanne on. TEST=Both Linux and Windows still boot and don't show ACPI errors on Mandolin after moving this inside the \_SB scope Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/mainboard/amd/bilby/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/google/zork/dsdt.asl M src/soc/amd/picasso/acpi/soc.asl 4 files changed, 27 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl index 140f395..dd42608 100644 --- a/src/mainboard/amd/bilby/dsdt.asl +++ b/src/mainboard/amd/bilby/dsdt.asl @@ -16,9 +16,6 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> - /* PCI IRQ mapping for the Southbridge */ - #include <pci_int_defs.asl> - /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 140f395..dd42608 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -16,9 +16,6 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> - /* PCI IRQ mapping for the Southbridge */ - #include <pci_int_defs.asl> - /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 732ebea..62520b9 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -17,9 +17,6 @@ #include <acpi/dsdt_top.asl> #include <globalnvs.asl> - /* PCI IRQ mapping for the Southbridge */ - #include <pci_int_defs.asl> - /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index c4425eb..f44f873 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -8,6 +8,9 @@ #include "sb_pci0_fch.asl" } +/* PCI IRQ mapping for the Southbridge */ +#include "pci_int_defs.asl" + /* Describe PCI INT[A-H] for the Southbridge */ #include <soc/amd/common/acpi/pci_int.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/69188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Gerrit-Change-Number: 69188 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
by Martin Roth (Code Review) 09 Nov '22

09 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69187 ) Change subject: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl ...................................................................... soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl This aligns Picasso more with the newer AMD SoCs and also makes it a bit clearer what this file does. Also remove the unneeded tabs at the beginning of each line. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/mainboard/amd/bilby/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/google/zork/dsdt.asl A src/soc/amd/picasso/acpi/pci_int_defs.asl D src/soc/amd/picasso/acpi/pcie.asl 5 files changed, 87 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Jason Glenesk: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl index e0059c9..140f395 100644 --- a/src/mainboard/amd/bilby/dsdt.asl +++ b/src/mainboard/amd/bilby/dsdt.asl @@ -17,7 +17,7 @@ #include <globalnvs.asl> /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> + #include <pci_int_defs.asl> /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index e0059c9..140f395 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -17,7 +17,7 @@ #include <globalnvs.asl> /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> + #include <pci_int_defs.asl> /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 3a92fe1..732ebea 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -18,7 +18,7 @@ #include <globalnvs.asl> /* PCI IRQ mapping for the Southbridge */ - #include <pcie.asl> + #include <pci_int_defs.asl> /* Power state notification to ALIB */ #include <pnot.asl> diff --git a/src/soc/amd/picasso/acpi/pci_int_defs.asl b/src/soc/amd/picasso/acpi/pci_int_defs.asl new file mode 100644 index 0000000..0e1a5b6 --- /dev/null +++ b/src/soc/amd/picasso/acpi/pci_int_defs.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* PCI IRQ mapping registers, C00h-C01h. */ +OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ +} +IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0: INTA */ + PIRB, 0x00000008, /* Index 1: INTB */ + PIRC, 0x00000008, /* Index 2: INTC */ + PIRD, 0x00000008, /* Index 3: INTD */ + PIRE, 0x00000008, /* Index 4: INTE */ + PIRF, 0x00000008, /* Index 5: INTF */ + PIRG, 0x00000008, /* Index 6: INTG */ + PIRH, 0x00000008, /* Index 7: INTH */ + + Offset (0x43), + PMMC, 0x00000008, /* Index 0x43: eMMC */ + + Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + + /* IO-APIC IRQs */ + Offset (0x80), + IORA, 0x00000008, /* Index 0x80: INTA */ + IORB, 0x00000008, /* Index 0x81: INTB */ + IORC, 0x00000008, /* Index 0x82: INTC */ + IORD, 0x00000008, /* Index 0x83: INTD */ + IORE, 0x00000008, /* Index 0x84: INTE */ + IORF, 0x00000008, /* Index 0x85: INTF */ + IORG, 0x00000008, /* Index 0x86: INTG */ + IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xC3), + IMMC, 0x00000008, /* Index 0xC3: eMMC */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ +} diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl deleted file mode 100644 index 601de52..0000000 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* PCI IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0: INTA */ - PIRB, 0x00000008, /* Index 1: INTB */ - PIRC, 0x00000008, /* Index 2: INTC */ - PIRD, 0x00000008, /* Index 3: INTD */ - PIRE, 0x00000008, /* Index 4: INTE */ - PIRF, 0x00000008, /* Index 5: INTF */ - PIRG, 0x00000008, /* Index 6: INTG */ - PIRH, 0x00000008, /* Index 7: INTH */ - - Offset (0x43), - PMMC, 0x00000008, /* Index 0x43: eMMC */ - - Offset (0x62), - PGPI, 0x00000008, /* Index 0x62: GPIO */ - - Offset (0x70), - PI20, 0x00000008, /* Index 0x70: I2C0 */ - PI21, 0x00000008, /* Index 0x71: I2C1 */ - PI22, 0x00000008, /* Index 0x72: I2C2 */ - PI23, 0x00000008, /* Index 0x73: I2C3 */ - PUA0, 0x00000008, /* Index 0x74: UART0 */ - PUA1, 0x00000008, /* Index 0x75: UART1 */ - PI24, 0x00000008, /* Index 0x76: I2C4 */ - PI25, 0x00000008, /* Index 0x77: I2C5 */ - PUA2, 0x00000008, /* Index 0x78: UART2 */ - PUA3, 0x00000008, /* Index 0x79: UART3 */ - - /* IO-APIC IRQs */ - Offset (0x80), - IORA, 0x00000008, /* Index 0x80: INTA */ - IORB, 0x00000008, /* Index 0x81: INTB */ - IORC, 0x00000008, /* Index 0x82: INTC */ - IORD, 0x00000008, /* Index 0x83: INTD */ - IORE, 0x00000008, /* Index 0x84: INTE */ - IORF, 0x00000008, /* Index 0x85: INTF */ - IORG, 0x00000008, /* Index 0x86: INTG */ - IORH, 0x00000008, /* Index 0x87: INTH */ - - Offset (0xC3), - IMMC, 0x00000008, /* Index 0xC3: eMMC */ - - Offset (0xE2), - IGPI, 0x00000008, /* Index 0xE2: GPIO */ - - Offset (0xF0), - II20, 0x00000008, /* Index 0xF0: I2C0 */ - II21, 0x00000008, /* Index 0xF1: I2C1 */ - II22, 0x00000008, /* Index 0xF2: I2C2 */ - II23, 0x00000008, /* Index 0xF3: I2C3 */ - IUA0, 0x00000008, /* Index 0xF4: UART0 */ - IUA1, 0x00000008, /* Index 0xF5: UART1 */ - II24, 0x00000008, /* Index 0xF6: I2C4 */ - II25, 0x00000008, /* Index 0xF7: I2C5 */ - IUA2, 0x00000008, /* Index 0xF8: UART2 */ - IUA3, 0x00000008, /* Index 0xF9: UART3 */ - } -- To view, visit https://review.coreboot.org/c/coreboot/+/69187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Gerrit-Change-Number: 69187 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/amd/chausie: Correct naming of EC FW
by Jason Glenesk (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Fred Reitberger, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69276 ) Change subject: mb/amd/chausie: Correct naming of EC FW ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53 Gerrit-Change-Number: 69276 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 15:44:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/morgana/Kconfig: Remove TODO after review
by Jason Glenesk (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Matt DeVillier, Fred Reitberger, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69275 ) Change subject: soc/amd/morgana/Kconfig: Remove TODO after review ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Gerrit-Change-Number: 69275 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 15:44:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/chausie/ec.c: Enable WLAN
by Jason Glenesk (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Fred Reitberger, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69319 ) Change subject: mb/amd/chausie/ec.c: Enable WLAN ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/chausie/ec.c: https://review.coreboot.org/c/coreboot/+/69319/comment/37200de6_8a485eeb PS1, Line 37: nit: extra line -- To view, visit https://review.coreboot.org/c/coreboot/+/69319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Gerrit-Change-Number: 69319 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Nov 2022 15:42:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
by Raul Rangel (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Jason Nien, Jon Murphy, Jan Dabros, Martin Roth, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67675 ) Change subject: mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb Gerrit-Change-Number: 67675 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 15:40:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022