coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347
by Nicholas Chin (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Angel Pons, Kyösti Mälkki. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68264 ) Change subject: drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347 ...................................................................... Patch Set 4: (1 comment) File src/drivers/usb/gadget.c: https://review.coreboot.org/c/coreboot/+/68264/comment/f628f5c8_d70ae139 PS4, Line 215: } __packed; > Are you conserned of endianess or sizeof() or something else? I guess what matters here is that those fields are in that order in a contiguous 7 byte area, and that the byte order is the same as what the USB CDC protocol expects. I'm assuming the EHCI debug stack just sends out whatever bytes it receives in the order they are received, and looking at a Wireshark dump of the USB CDC packet it appears that the 32-bit baud rate is sent LSB so I guess endianness could be an issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/68264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9 Gerrit-Change-Number: 68264 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 22:27:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
by Kyösti Mälkki (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Chen-Tsung Hsieh, Martin L Roth, Macpaul Lin, Julius Werner, Yu-Ping Wu. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66625 ) Change subject: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... Patch Set 7: Code-Review+1 (1 comment) Patchset: PS7: Fine with me. -- To view, visit https://review.coreboot.org/c/coreboot/+/66625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Gerrit-Change-Number: 66625 Gerrit-PatchSet: 7 Gerrit-Owner: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 22:12:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347
by Kyösti Mälkki (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Angel Pons, Nicholas Chin. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68264 ) Change subject: drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347 ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/drivers/usb/gadget.c: https://review.coreboot.org/c/coreboot/+/68264/comment/064a3346_7a52078a PS4, Line 215: } __packed; > This might not be portable. Are you conserned of endianess or sizeof() or something else? -- To view, visit https://review.coreboot.org/c/coreboot/+/68264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9 Gerrit-Change-Number: 68264 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 22:06:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/agah: Add Power Limits for RPL SKU
by Tarun Tuli (Code Review) 09 Nov '22

09 Nov '22

Tarun Tuli has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69419 ) Change subject: mb/google/brya/agah: Add Power Limits for RPL SKU ...................................................................... mb/google/brya/agah: Add Power Limits for RPL SKU Add power limits for the RPL SKUs of Agah BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/variants/agah/Makefile.inc A src/mainboard/google/brya/variants/agah/ramstage.c 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/69419/1 diff --git a/src/mainboard/google/brya/variants/agah/Makefile.inc b/src/mainboard/google/brya/variants/agah/Makefile.inc index 3d5212f..2c607bf 100644 --- a/src/mainboard/google/brya/variants/agah/Makefile.inc +++ b/src/mainboard/google/brya/variants/agah/Makefile.inc @@ -7,3 +7,4 @@ ramstage-y += gpio.c ramstage-y += variant.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/agah/ramstage.c b/src/mainboard/google/brya/variants/agah/ramstage.c new file mode 100644 index 0000000..2aa9ec8 --- /dev/null +++ b/src/mainboard/google/brya/variants/agah/ramstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for baseline config as per bug:191906315 comment #10 */ + { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 }, + /* Following values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Gerrit-Change-Number: 69419 Gerrit-PatchSet: 1 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/agah: Add RPL Support to Agah
by Tarun Tuli (Code Review) 09 Nov '22

09 Nov '22

Tarun Tuli has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69398 ) Change subject: mb/google/brya/agah: Add RPL Support to Agah ...................................................................... mb/google/brya/agah: Add RPL Support to Agah Enable RPL support for Agah BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69398/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 2102961..de981ff 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -3,6 +3,7 @@ config BOARD_GOOGLE_AGAH bool "-> Agah" select BOARD_GOOGLE_BASEBOARD_BRYA + select SOC_INTEL_RAPTORLAKE select DRIVERS_GENESYSLOGIC_GL9750 select INCLUDE_NVIDIA_GPU_ASL select PCIEXP_SUPPORT_RESIZABLE_BARS -- To view, visit https://review.coreboot.org/c/coreboot/+/69398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5437dbf9e7812367a280d1ed659f286fb9b62a68 Gerrit-Change-Number: 69398 Gerrit-PatchSet: 1 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz
by 9elements QA (Code Review) 09 Nov '22

09 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69305 ) Change subject: soc/intel/elkhartlake: Correct I2C base clock to 100 MHz ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135265 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135264 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135263 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135262 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135261 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135260 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135259 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135258 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135257 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135256 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135255 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135254 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135253 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135252 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135251 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135250 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2 Gerrit-Change-Number: 69305 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 21:49:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/fsp2: Don't die if the FSP signature doesn't match
by Martin L Roth (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Andrey Petrov. Hello Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69412 to look at the new patch set (#2). Change subject: drivers/fsp2: Don't die if the FSP signature doesn't match ...................................................................... drivers/fsp2: Don't die if the FSP signature doesn't match If the FSP signature doesn't match, there's going to be something else that kills the system, or not. Either way, killing the system in coreboot isn't needed. We should absolutely print an error message, but let the FSP take care of halting the system or better still, returning to let coreboot print a message and halt at that point. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I12aca7cad3298ac36b1fed09efaa190c958cf126 --- M src/drivers/intel/fsp2_0/util.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/69412/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12aca7cad3298ac36b1fed09efaa190c958cf126 Gerrit-Change-Number: 69412 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/fsp2: Don't die if the FSP signature doesn't match
by build bot (Jenkins) (Code Review) 09 Nov '22

09 Nov '22

Attention is currently required from: Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69412 ) Change subject: drivers/fsp2: Don't die if the FSP signature doesn't match ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163124): https://review.coreboot.org/c/coreboot/+/69412/comment/3ce65a79_a17a4fc1 PS1, Line 11: coreboot isn't needed. We should absolutely print an error message, but Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12aca7cad3298ac36b1fed09efaa190c958cf126 Gerrit-Change-Number: 69412 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 21:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/fsp2: Don't die if the FSP signature doesn't match
by Martin L Roth (Code Review) 09 Nov '22

09 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69412 ) Change subject: drivers/fsp2: Don't die if the FSP signature doesn't match ...................................................................... drivers/fsp2: Don't die if the FSP signature doesn't match If the FSP signature doesn't match, there's going to be something else that kills the system, or not. Either way, killing the system in coreboot isn't needed. We should absolutely print an error message, but let the FSP take care of halting the system or better still, returning to let coreboot print a message and halt at that point. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I12aca7cad3298ac36b1fed09efaa190c958cf126 --- M src/drivers/intel/fsp2_0/util.c 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/69412/1 diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 1dedb65..1f8e12f 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -182,7 +182,7 @@ if (upd_signature != expected_signature) { /* The UPD signatures are non-zero-terminated ASCII stored as a little endian uint64_t, so this needs some casts. */ - die_with_post_code(POST_INVALID_VENDOR_BINARY, + printk(BIOS_EMERG, "Invalid UPD signature! FSP provided \"%8s\", expected was \"%8s\".\n", (char *)&upd_signature, (char *)&expected_signature); -- To view, visit https://review.coreboot.org/c/coreboot/+/69412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12aca7cad3298ac36b1fed09efaa190c958cf126 Gerrit-Change-Number: 69412 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common/xhci: Fix building for 64bit
by 9elements QA (Code Review) 09 Nov '22

09 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69234 ) Change subject: soc/intel/common/xhci: Fix building for 64bit ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135233 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135232 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135231 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135230 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135229 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135228 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135227 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135226 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135225 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135224 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135223 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135222 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135221 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135220 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135219 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135218 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66392bcb4ed94c97dde43342dd29dab15d1dd9ea Gerrit-Change-Number: 69234 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 21:26:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2022