coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: device/xhci: Factor out `struct xhci_usb_info`
by Martin L Roth (Code Review) 10 Nov '22

10 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67934 ) Change subject: device/xhci: Factor out `struct xhci_usb_info` ...................................................................... device/xhci: Factor out `struct xhci_usb_info` This commit factors out `struct xhci_usb_info` from intel specific code as it will be useful on other platforms. BUG=b:186792595 TEST=Builds for volteer Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/include/device/xhci.h M src/soc/intel/common/block/include/intelblocks/xhci.h 2 files changed, 34 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h index e5ce8b5..a4a3bc1 100644 --- a/src/include/device/xhci.h +++ b/src/include/device/xhci.h @@ -81,6 +81,20 @@ }; }; +/* + * struct xhci_usb_info - Data containing number of USB ports & offset. + * @usb2_port_status_reg: Offset to USB2 port status register. + * @num_usb2_ports: Number of USB2 ports. + * @usb3_port_status_reg: Offset to USB3 port status register. + * @num_usb3_ports: Number of USB3 ports. + */ +struct xhci_usb_info { + uint32_t usb2_port_status_reg; + uint32_t num_usb2_ports; + uint32_t usb3_port_status_reg; + uint32_t num_usb3_ports; +}; + /** * Iterates over the xHCI Extended Capabilities List. */ diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 7e2b76e..8c58891 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -4,24 +4,11 @@ #define SOC_INTEL_COMMON_BLOCK_XHCI_H #include <device/device.h> +#include <device/xhci.h> #include <elog.h> #include <stdint.h> /* - * struct xhci_usb_info - Data containing number of USB ports & offset. - * @usb2_port_status_reg: Offset to USB2 port status register. - * @num_usb2_ports: Number of USB2 ports. - * @usb3_port_status_reg: Offset to USB3 port status register. - * @num_usb3_ports: Number of USB3 ports. - */ -struct xhci_usb_info { - uint32_t usb2_port_status_reg; - uint32_t num_usb2_ports; - uint32_t usb3_port_status_reg; - uint32_t num_usb3_ports; -}; - -/* * struct xhci_wake_info - Relates an XHCI device to registers and wake types * @xhci_dev: devfn of the XHCI device * @elog_wake_type_host: the wake type for the controller device -- To view, visit https://review.coreboot.org/c/coreboot/+/67934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Gerrit-Change-Number: 67934 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: device/xhci: Factor out common PORTSC code
by Martin L Roth (Code Review) 10 Nov '22

10 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67933 ) Change subject: device/xhci: Factor out common PORTSC code ...................................................................... device/xhci: Factor out common PORTSC code This commit factors out some code for XHCI port status values. BUG=b:186792595 TEST=Built coreboot for volteer device Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/xhci.h M src/soc/intel/common/block/xhci/elog.c 2 files changed, 61 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h index 17ce846..e5ce8b5 100644 --- a/src/include/device/xhci.h +++ b/src/include/device/xhci.h @@ -3,7 +3,7 @@ #ifndef __DEVICE_XHCI_H__ #define __DEVICE_XHCI_H__ -#include <stdint.h> +#include <types.h> #include <device/device.h> #include <commonlib/bsd/cb_err.h> @@ -12,6 +12,42 @@ #define XHCI_ECP_CAP_ID_LEGACY 1 #define XHCI_ECP_CAP_ID_SUPP 2 +/* Status flags */ +/* Wake on disconnect enable */ +#define XHCI_STATUS_WDE BIT(26) +/* Wake on connect enable */ +#define XHCI_STATUS_WCE BIT(25) +/* Port link status change */ +#define XHCI_STATUS_PLC BIT(22) +/* Connect status change */ +#define XHCI_STATUS_CSC BIT(17) +/* Port link status */ +#define XHCI_STATUS_PLS_SHIFT 5 +#define XHCI_STATUS_PLS_MASK (0xf << XHCI_STATUS_PLS_SHIFT) +#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT) + +static inline bool xhci_portsc_csc(uint32_t port_status) +{ + return port_status & XHCI_STATUS_CSC; +} + +static inline bool xhci_portsc_wake_capable(uint32_t port_status) +{ + return (port_status & XHCI_STATUS_WCE) | + (port_status & XHCI_STATUS_WDE); +} + +static inline bool xhci_portsc_plc(uint32_t port_status) +{ + return port_status & XHCI_STATUS_PLC; +} + +static inline bool xhci_portsc_resume(uint32_t port_status) +{ + return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME; +} + + struct xhci_supported_protocol { union { uint32_t reg0; diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c index e6a1c0f..8acefba 100644 --- a/src/soc/intel/common/block/xhci/elog.c +++ b/src/soc/intel/common/block/xhci/elog.c @@ -2,45 +2,12 @@ #include <device/mmio.h> #include <device/pci_ops.h> +#include <device/xhci.h> #include <elog.h> #include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <stdint.h> -/* Wake on disconnect enable */ -#define XHCI_STATUS_WDE (1 << 26) -/* Wake on connect enable */ -#define XHCI_STATUS_WCE (1 << 25) -/* Port link status change */ -#define XHCI_STATUS_PLC (1 << 22) -/* Connect status change */ -#define XHCI_STATUS_CSC (1 << 17) -/* Port link status */ -#define XHCI_STATUS_PLS_SHIFT (5) -#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT) -#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT) - -static bool xhci_csc_set(uint32_t port_status) -{ - return !!(port_status & XHCI_STATUS_CSC); -} - -static bool xhci_wake_capable(uint32_t port_status) -{ - return !!((port_status & XHCI_STATUS_WCE) | - (port_status & XHCI_STATUS_WDE)); -} - -static bool xhci_plc_set(uint32_t port_status) -{ - return !!(port_status & XHCI_STATUS_PLC); -} - -static bool xhci_resume(uint32_t port_status) -{ - return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME; -} - /* * Check if a particular USB port caused wake by: * 1. Change in connect/disconnect status (if enabled) @@ -73,8 +40,8 @@ * connect/disconnect to identify if the port caused wake * event for USB attach/detach. */ - if (xhci_csc_set(port_status) && - xhci_wake_capable(port_status)) { + if (xhci_portsc_csc(port_status) && + xhci_portsc_wake_capable(port_status)) { elog_add_event_wake(host_event, 0); elog_add_event_wake(event, i + 1); found = true; @@ -85,8 +52,8 @@ * Check if PLC is set and PLS indicates resume to identify if * the port caused wake event for USB activity. */ - if (xhci_plc_set(port_status) && - xhci_resume(port_status)) { + if (xhci_portsc_plc(port_status) && + xhci_portsc_resume(port_status)) { elog_add_event_wake(host_event, 0); elog_add_event_wake(event, i + 1); found = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/67933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Gerrit-Change-Number: 67933 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: device/pciexp: add pcie_find_dsn()
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jonathan Zhang, Stefan Reinauer, David Hendricks, Subrata Banik, Angel Pons, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54510 ) Change subject: device/pciexp: add pcie_find_dsn() ...................................................................... Patch Set 13: (1 comment) File src/device/pciexp_device.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163129): https://review.coreboot.org/c/coreboot/+/54510/comment/9b8ca818_91abfdba PS13, Line 99: * @param serial Serial number of the device. Possible repeated word: 'serial' -- To view, visit https://review.coreboot.org/c/coreboot/+/54510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618b Gerrit-Change-Number: 54510 Gerrit-PatchSet: 13 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 23:33:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: device/pciexp: add pcie_find_dsn()
by Jonathan Zhang (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jonathan Zhang, Stefan Reinauer, David Hendricks, Subrata Banik, Angel Pons, ron minnich. Hello build bot (Jenkins), Stefan Reinauer, David Hendricks, Subrata Banik, Angel Pons, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54510 to look at the new patch set (#13). Change subject: device/pciexp: add pcie_find_dsn() ...................................................................... device/pciexp: add pcie_find_dsn() Add pcie_find_dsn() to detect and match PCIe device serial number. In addition, vendor ID is matched when provided. Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54510/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/54510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618b Gerrit-Change-Number: 54510 Gerrit-PatchSet: 13 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: device/pciexp: add pcie_find_dsn()
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jonathan Zhang, Stefan Reinauer, David Hendricks, Subrata Banik, Angel Pons, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54510 ) Change subject: device/pciexp: add pcie_find_dsn() ...................................................................... Patch Set 12: (1 comment) File src/device/pciexp_device.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163128): https://review.coreboot.org/c/coreboot/+/54510/comment/b46ec260_4f80227b PS12, Line 99: * @param serial Serial number of the device. Possible repeated word: 'serial' -- To view, visit https://review.coreboot.org/c/coreboot/+/54510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618b Gerrit-Change-Number: 54510 Gerrit-PatchSet: 12 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 23:31:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: device/pciexp: add pcie_find_dsn()
by Jonathan Zhang (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jonathan Zhang, Stefan Reinauer, David Hendricks, Subrata Banik, Angel Pons, ron minnich. Hello build bot (Jenkins), Stefan Reinauer, David Hendricks, Subrata Banik, Angel Pons, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54510 to look at the new patch set (#12). Change subject: device/pciexp: add pcie_find_dsn() ...................................................................... device/pciexp: add pcie_find_dsn() Add pcie_find_dsn() to detect and match PCIe device serial number. In addition, vendor ID is matched when provided. Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> --- M src/device/pciexp_device.c M src/include/device/pciexp.h 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54510/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/54510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618b Gerrit-Change-Number: 54510 Gerrit-PatchSet: 12 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: David Hendricks Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69188 ) Change subject: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135297 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135296 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135295 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135294 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135293 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135292 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135291 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135290 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135289 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135288 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135287 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135286 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135285 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135284 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135283 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135282 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f Gerrit-Change-Number: 69188 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 23:22:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69187 ) Change subject: soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135281 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135280 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135279 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135278 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135277 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135276 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135275 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135274 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135273 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135272 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135271 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135270 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135269 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135268 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135267 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135266 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8 Gerrit-Change-Number: 69187 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Nov 2022 22:47:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config
by Raul Rangel (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Martin Roth, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68942 ) Change subject: mb/google/skyrim/var/winterhold: Define Dynamic DPTC config ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/68942/comment/6e8d7ddc_390642ba PS8, Line 146: FEATURE_DYNAMIC_DPTC Merge this with the CL that actually implements this -- To view, visit https://review.coreboot.org/c/coreboot/+/68942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3db70c151f962184e0475a8d11a51568f4b8ced3 Gerrit-Change-Number: 68942 Gerrit-PatchSet: 8 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Nov 2022 22:37:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: ec/google/chromec: Expand EC share memory for DTTS
by Raul Rangel (Code Review) 10 Nov '22

10 Nov '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68077 ) ( 24 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/google/chromec: Expand EC share memory for DTTS ...................................................................... ec/google/chromec: Expand EC share memory for DTTS DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Van Patten: Looks good to me, but someone else must approve diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 0914fdd..3200902 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -56,6 +56,7 @@ CHGL, 8, // Charger Current Limit TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number + STTB, 1, // Switch thermal table by body detection status // DFUD must be 0 for the other 31 values to be valid Offset (0x0a), DFUD, 1, // Device Features Undefined -- To view, visit https://review.coreboot.org/c/coreboot/+/68077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Gerrit-Change-Number: 68077 Gerrit-PatchSet: 27 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022