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Change subject: mb/google/brya/var/gladios: Add GL9750 SD card reader support
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Patch Set 3: Code-Review+2
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Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Please review the latest patchset
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/69324/comment/3f1a3730_1d469dbb
PS1, Line 141: hfsts1.fields.mfg_mode
> I see your point that it's a bit arbitrary exactly which conditions the Manufacturing Mode log shoul […]
Marking this resolved. Feel free to reopen.
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Change subject: mb/google/brya/var/gladios: Add GL9750 SD card reader support
......................................................................
mb/google/brya/var/gladios: Add GL9750 SD card reader support
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
---
M src/mainboard/google/brya/Kconfig.name
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/69436/3
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Change subject: mb/google/brya/var/gladios: Add GL9750 SD card reader support
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> same CL? https://review.coreboot. […]
no, GL9750 is for SD card reader
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/var/gladios: Add GL9750 SD card reader support
......................................................................
mb/google/brya/var/gladios: Add GL9750 SD card reader support
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0
---
M src/mainboard/google/brya/Kconfig.name
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/69436/2
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Change subject: ec/google/chromeec: Simplify get_uptime_info error handling
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Patch Set 3: Code-Review+2
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Change subject: ec/google/chromeec: Simplify error handling for GET_VERSION
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Change subject: mb/google/brya: add missing devices to DSDT
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69392/comment/3de1a667_67bd0b7a
PS4, Line 10: SHA
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07
File src/mainboard/google/brya/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/69392/comment/331a1c32_1580abd5
PS4, Line 32: Device (FSPI) {}
> Would it make sense to move these into their respective device . […]
Those looks like the Intel device APCI. And should include when enable the device in device tree. Better let Intel check the soc level code.
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