coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/amd/morgana: Add 32M support
by Bao Zheng (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69150 ) Change subject: soc/amd/morgana: Add 32M support ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > This change makes so many assumptions about how things are going to work, and breaks so many current […] So where should the AMDFW and coreboot be located for Birman? The AMDFW should be at relative 0x20000, which is defined by HW. So it should be at bottom 16M. The coreboot stages should be upper 16M, otherwise the running address pointer and data loading don't have the correct address. So how is the amdfw "inside" CBFS? -- To view, visit https://review.coreboot.org/c/coreboot/+/69150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140 Gerrit-Change-Number: 69150 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Nov 2022 03:18:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
by Yidi Lin (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Chen-Tsung Hsieh, Martin L Roth, Macpaul Lin, Julius Werner, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66625 ) Change subject: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/66625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Gerrit-Change-Number: 66625 Gerrit-PatchSet: 9 Gerrit-Owner: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:56:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/gladios: Update gpio table
by Kevin Chiu (Code Review) 11 Nov '22

11 Nov '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69463 ) Change subject: mb/google/brya/var/gladios: Update gpio table ...................................................................... mb/google/brya/var/gladios: Update gpio table Based on the latest schematic to update the gpio table. BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f --- A src/mainboard/google/brya/variants/gladios/Makefile.inc A src/mainboard/google/brya/variants/gladios/gpio.c 2 files changed, 182 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/69463/1 diff --git a/src/mainboard/google/brya/variants/gladios/Makefile.inc b/src/mainboard/google/brya/variants/gladios/Makefile.inc new file mode 100644 index 0000000..d38141c --- /dev/null +++ b/src/mainboard/google/brya/variants/gladios/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/gladios/gpio.c b/src/mainboard/google/brya/variants/gladios/gpio.c new file mode 100644 index 0000000..1dfef5c --- /dev/null +++ b/src/mainboard/google/brya/variants/gladios/gpio.c @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> NC */ + PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG), + /* A15 : USB_OC2# ==> NC */ + PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG), + /* A18 : DDSP_HPDB ==> HDMIB_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), + + /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPI */ + PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD ==> NC */ + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), + + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E14 : DDSP_HPDA ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* H19 : SRCCLKREQ4# ==> CLKREQ_4 */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H21 : IMGCLKOUT2 ==> EMMC_PE_WAKE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 0, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaf0629dcd77d21cf09fe84e760f1f22c075467f Gerrit-Change-Number: 69463 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
by Rex-BC Chen (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Chen-Tsung Hsieh, Martin L Roth, Macpaul Lin, Julius Werner, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66625 ) Change subject: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/66625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Gerrit-Change-Number: 66625 Gerrit-PatchSet: 9 Gerrit-Owner: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:55:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
by Macpaul Lin (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Chen-Tsung Hsieh, Martin L Roth, Julius Werner, Yu-Ping Wu, Yidi Lin. Macpaul Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66625 ) Change subject: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... Patch Set 9: (1 comment) Patchset: PS6: > now that all contributors have agreed, this should be good to go Done -- To view, visit https://review.coreboot.org/c/coreboot/+/66625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Gerrit-Change-Number: 66625 Gerrit-PatchSet: 9 Gerrit-Owner: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:51:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)chromium.org> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Macpaul Lin <macpaul.lin(a)mediatek.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT
by Macpaul Lin (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Chen-Tsung Hsieh, Martin L Roth, Julius Werner, Yidi Lin. Macpaul Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66625 ) Change subject: soc/mediatek/mt8195: replace SPDX identifiers to GPL-2.0-only OR MIT ...................................................................... Patch Set 9: Code-Review+1 (1 comment) Patchset: PS7: > Thanks you all! […] Found conflict files were moved to src/soc/mediatek/common/dp. src/soc/mediatek/mt8195/dptx.c src/soc/mediatek/mt8195/dptx_hal.c src/soc/mediatek/mt8195/include/soc/dp_intf.h src/soc/mediatek/mt8195/include/soc/dptx.h src/soc/mediatek/mt8195/include/soc/dptx_hal.h src/soc/mediatek/mt8195/include/soc/dptx_reg.h Will send a separate patch for common drivers. So remove these files in this patch to solve the conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/66625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52 Gerrit-Change-Number: 66625 Gerrit-PatchSet: 9 Gerrit-Owner: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Macpaul Lin <macpaul.lin(a)mediatek.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: use RPL FSP headers
by 9elements QA (Code Review) 11 Nov '22

11 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69367 ) Change subject: mb/google/brya/var/marasov: use RPL FSP headers ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135659 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135658 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135657 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135656 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135655 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135654 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135653 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135652 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135651 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135650 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135649 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135648 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135647 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135646 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135645 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135644 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7874420c0fb51b9cc616cd979ffc9349c381602e Gerrit-Change-Number: 69367 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:45:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common: Definition of EFS_OFFSET
by build bot (Jenkins) (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69462 ) Change subject: soc/amd/common: Definition of EFS_OFFSET ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/include/amdblocks/psp_efs.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163255): https://review.coreboot.org/c/coreboot/+/69462/comment/568dac64_982e64fc PS1, Line 10: #define EFS_OFFSET ((0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1) - (FMAP_SECTION_FLASH_START & 0xffffff)) line length of 130 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/69462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I915c43d38c09fbb5c7835f139d0c1a4e8526aeec Gerrit-Change-Number: 69462 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:31:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdfwtool: Add definition of instance for PSP entry
by build bot (Jenkins) (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69044 ) Change subject: amdfwtool: Add definition of instance for PSP entry ...................................................................... Patch Set 6: (1 comment) File util/amdfwtool/amdfwtool.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163251): https://review.coreboot.org/c/coreboot/+/69044/comment/08efccc2_a4da22ad PS6, Line 166: } __attribute__((packed)); Prefer __packed over __attribute__((packed)) -- To view, visit https://review.coreboot.org/c/coreboot/+/69044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Gerrit-Change-Number: 69044 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:29:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: amdfwtool: Set the base address of AMDFW as relative
by build bot (Jenkins) (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69429 ) Change subject: amdfwtool: Set the base address of AMDFW as relative ...................................................................... Patch Set 3: (7 comments) File util/amdfwtool/amdfwtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/3245b697_90d468aa PS3, Line 2294: case 0: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/b3e168fe_84c9de4f PS3, Line 2295: case 0xFA0000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/a6bdf53a_9775d4dc PS3, Line 2296: case 0xF20000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/a44a78a0_dcd2f887 PS3, Line 2297: case 0xE20000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/d7173775_7e15ff3b PS3, Line 2298: case 0xC20000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/66560bac_b740c203 PS3, Line 2299: case 0x820000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163249): https://review.coreboot.org/c/coreboot/+/69429/comment/044e6746_c48d7b34 PS3, Line 2300: case 0x020000: /* Fall through */ Prefer 'fallthrough;' over fallthrough comment -- To view, visit https://review.coreboot.org/c/coreboot/+/69429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6fd5b21be90ac37618c484506db9b8a1e350ea2 Gerrit-Change-Number: 69429 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Nov 2022 02:29:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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