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Change in coreboot[master]: [TESTME]lenovo/x220: Attempt to fix broken DRAM init
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39043 ) Change subject: [TESTME]lenovo/x220: Attempt to fix broken DRAM init ...................................................................... [TESTME]lenovo/x220: Attempt to fix broken DRAM init Enable power on WWAN as it has SMBUS connected. Might resolv an issue where DRAM init fails as no EEPROM is found on the bus. Untested. Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/ec/lenovo/h8/Makefile.inc M src/mainboard/lenovo/x220/early_init.c 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39043/1 diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 51c11be..9c8687a 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -18,6 +18,8 @@ ramstage-y += panic.c endif +romstage += wwan.c + ramstage-y += h8.c ramstage-y += bluetooth.c ramstage-y += wwan.c diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 3429c1b..ae16f0c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -24,6 +24,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <cpu/x86/msr.h> +#include <ec/lenovo/h8/h8.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -74,6 +75,18 @@ *pei_data = pei_data_template; } +void mainboard_early_init(int s3_resume) +{ + /* + * The WWAN slot has SMBUS connected. Turn on power to make sure + * SMBUS is usable and DRAM init will succeed. + * ramstage will turn it off, in case it's not needed. + * TODO: Does GPIO42 (SMB_3B_EN) help here? + */ + if (h8_has_wwan()) + h8_wwan_enable(true); +} + void mainboard_get_spd(spd_raw_data *spd, bool id_only) { read_spd (&spd[0], 0x50, id_only); -- To view, visit https://review.coreboot.org/c/coreboot/+/39043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a2ca370124ecf743b000998b56855d5ed8f573 Gerrit-Change-Number: 39043 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: amdfwtool: Use *number in config file as NVRAM entry
by Bao Zheng (Code Review) 07 Aug '23

07 Aug '23

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49015 to review the following change. Change subject: amdfwtool: Use *number in config file as NVRAM entry ...................................................................... amdfwtool: Use *number in config file as NVRAM entry Add the entry like XXXX_FW_TYPE_STRING *0xXXXXX to config file. Then the required size of space will be allocated related to the firmware type. Change-Id: I98c94b4087f8a174f7d5753a30695a10f1b796ae Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 6 files changed, 35 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/49015/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index a0f3ec4..08d2817 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -213,7 +213,7 @@ # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_APCB_FILES_BK) \ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 969f512..f7ef699 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -141,7 +141,7 @@ # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 215a5a1..3d96823 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -110,7 +110,7 @@ # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f167e5e..b6c9c8d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -775,6 +775,13 @@ ctx->current = ALIGN(ctx->current + bytes, BLOB_ALIGNMENT); count++; + } else if (fw_table[i].blank_size != 0) { + pspdir->entries[count].type = fw_table[i].type; + pspdir->entries[count].subprog = fw_table[i].subprog; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = (uint32_t)fw_table[i].blank_size; + pspdir->entries[count].addr = RUN_CURRENT(*ctx); + count++; } else { /* This APU doesn't have this firmware. */ } @@ -1018,11 +1025,15 @@ fw_table[i].type == AMD_BIOS_APCB_BK) ctx->current = ALIGN( ctx->current, ERASE_ALIGNMENT); - bytes = copy_blob(BUFF_CURRENT(*ctx), - fw_table[i].filename, BUFF_ROOM(*ctx)); - if (bytes <= 0) { - free(ctx->rom); - exit(1); + if (fw_table[i].filename != NULL) { + bytes = copy_blob(BUFF_CURRENT(*ctx), + fw_table[i].filename, BUFF_ROOM(*ctx)); + if (bytes <= 0) { + free(ctx->rom); + exit(1); + } + } else if (fw_table[i].blank_size != 0){ + bytes = fw_table[i].blank_size; } biosdir->entries[count].size = (uint32_t)bytes; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 6ae4675..beaa360 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -109,6 +109,7 @@ uint8_t subprog; int level; uint64_t other; + uint32_t blank_size; } amd_fw_entry; typedef struct _amd_cb_config { diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 017c689..de31242 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -254,7 +254,10 @@ while (psp_tableptr->type != AMD_FW_INVALID) { /* instance are not used in PSP table */ if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog) { - psp_tableptr->filename = filename; + if (filename[0] == '*') + psp_tableptr->blank_size = strtoull(&filename[1], NULL, 16); + else + psp_tableptr->filename = filename; break; } psp_tableptr++; @@ -330,7 +333,10 @@ if (bhd_tableptr->type == fw_type && bhd_tableptr->subpr == subprog && bhd_tableptr->inst == instance) { - bhd_tableptr->filename = filename; + if (filename[0] == '*') + bhd_tableptr->blank_size = strtoull(&filename[1], NULL, 16); + else + bhd_tableptr->filename = filename; break; } bhd_tableptr++; @@ -440,9 +446,13 @@ continue; } else { path_filename = malloc(MAX_LINE_SIZE); - strcpy(path_filename, dir); - strcat(path_filename, "/"); - strcat(path_filename, &(oneline[match[2].rm_so])); + if (oneline[match[2].rm_so] == '*') { + strcpy(path_filename, &(oneline[match[2].rm_so])); + } else { + strcpy(path_filename, dir); + strcat(path_filename, "/"); + strcat(path_filename, &(oneline[match[2].rm_so])); + } if (find_register_fw_filename_psp_dir( &(oneline[match[1].rm_so]), -- To view, visit https://review.coreboot.org/c/coreboot/+/49015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98c94b4087f8a174f7d5753a30695a10f1b796ae Gerrit-Change-Number: 49015 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

5 53

Change in coreboot[master]: sb/intel/lynxpoint: Setup gpio in bootblock
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36712 ) Change subject: sb/intel/lynxpoint: Setup gpio in bootblock ...................................................................... sb/intel/lynxpoint: Setup gpio in bootblock GPIO setup is needed for verstage. verstage can also still happen after romstage so keep the GPIO init there too. Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/h81m-hds/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/slippy/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/mainboard/supermicro/x10slm-f/Makefile.inc M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36712/1 diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc index de18bc5..3fc7ac7 100644 --- a/src/mainboard/asrock/h81m-hds/Makefile.inc +++ b/src/mainboard/asrock/h81m-hds/Makefile.inc @@ -16,4 +16,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 7535350..0ecb31d 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -23,5 +23,7 @@ romstage-y += variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index f80dcab..e35f93e 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -23,6 +23,8 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 91a7963..8f12999 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +bootblock-y += gpio.c romstage-y += gpio.c smm-y += mainboard_smi.c diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc index 301070b..0b4f367 100644 --- a/src/mainboard/supermicro/x10slm-f/Makefile.inc +++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc @@ -15,4 +15,5 @@ ## romstage-y += gpio.c +bootblock-y += gpio.c bootblock-y += bootblock.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5ca7daf..433a310 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index e53ed8d..bacaf74 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -50,6 +50,7 @@ romstage-y += rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) +bootblock-y += lp_gpio.c romstage-y += lp_gpio.c ramstage-y += lp_gpio.c smm-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 39e6925..abcb35b 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "pch.h" +#include "lp_gpio.h" /* * Enable Prefetching and Caching. @@ -33,14 +34,6 @@ pci_write_config8(dev, 0xdc, reg8); } - -static void map_rcba(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -} - static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by default, @@ -72,7 +65,7 @@ void bootblock_early_southbridge_init(void) { - map_rcba(); + pch_enable_bars(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); @@ -83,3 +76,12 @@ pch_enable_lpc(); mainboard_config_superio(); } + +void bootblock_southbridge_init(void) +{ +#if CONFIG(INTEL_LYNXPOINT_LP) + setup_pch_lp_gpios(mainboard_gpio_map); +#else + setup_pch_gpios(mainboard_gpio_map); +#endif +} diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index b49d3cf..9cf021e 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -45,7 +45,7 @@ return id == PCH_TYPE_LPT_LP; } -static void pch_enable_bars(void) +void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8802be1..561c5b7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -184,6 +184,7 @@ int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); +void pch_enable_bars(void); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I448ca12f5ddab362983429c508e518b7042ef760 Gerrit-Change-Number: 36712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s)
by Bill XIE (Code Review) 07 Aug '23

07 Aug '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48771 ) Change subject: mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s) ...................................................................... mainboard/lenovo: Add Thinkpad Edge S220 (a.k.a E220s) The code is based on autoport and that for s230u Tested: - CPU i3-2357M - Slotted DIMM 2GiB - Camera - pci-e and usb2 on Mini PCI-E slot for wlan - sata and usb2 on Mini PCI-E slot for wwan - On board SDHCI connected to pci-e - libgfxinit-based graphic init - Sound - S3 - EHCI debug - Seabios Payload Change-Id: I746798b13e83d1971bb7be93751a15875d16c337 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/s220.md A Documentation/mainboard/lenovo/s220_ready_to_flash.jpg M src/mainboard/hp/snb_ivb_laptops/cmos.default A src/mainboard/lenovo/s220/Kconfig A src/mainboard/lenovo/s220/Kconfig.name A src/mainboard/lenovo/s220/Makefile.inc A src/mainboard/lenovo/s220/acpi/ec.asl A src/mainboard/lenovo/s220/acpi/gpe.asl A src/mainboard/lenovo/s220/acpi/platform.asl A src/mainboard/lenovo/s220/acpi/superio.asl A src/mainboard/lenovo/s220/acpi_tables.c A src/mainboard/lenovo/s220/board_info.txt A src/mainboard/lenovo/s220/data.vbt A src/mainboard/lenovo/s220/devicetree.cb A src/mainboard/lenovo/s220/dsdt.asl A src/mainboard/lenovo/s220/early_init.c A src/mainboard/lenovo/s220/ec.c A src/mainboard/lenovo/s220/ec.h A src/mainboard/lenovo/s220/gma-mainboard.ads A src/mainboard/lenovo/s220/gpio.c A src/mainboard/lenovo/s220/hda_verb.c A src/mainboard/lenovo/s220/mainboard.c A src/mainboard/lenovo/s220/smihandler.c 24 files changed, 1,269 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48771/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55..c0976e0 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -103,6 +103,7 @@ - [T420](lenovo/t420.md) - [T420 / T520 / X220 / T420s / W520 common](lenovo/Sandy_Bridge_series.md) - [X1](lenovo/x1.md) +- [S220](lenovo/s220.md) ### Ivy Bridge series diff --git a/Documentation/mainboard/lenovo/s220.md b/Documentation/mainboard/lenovo/s220.md new file mode 100644 index 0000000..2bbc22d --- /dev/null +++ b/Documentation/mainboard/lenovo/s220.md @@ -0,0 +1,36 @@ +# Lenovo Edge S220 (a.k.a E220s) + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + +![S220 ready to flash](s220_ready_to_flash.jpg) + +* Keyboard +* Hard Drive Cover +* Palmrest + +Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/e220s_s220_hmm_en_0a60672… can be used as a guidance of disassembly. + +The vendor IFD VSCC list contains: +- MACRONIX_MX25L6405 (0xc2, 0x2017) +- WINBOND_NEX_W25X64 (0xef, 0x3017) +- ATMEL_AT25DF641 (0x1f, 0x4800) + +The general [flashing tutorial] has more details. + +Tested: +- CPU i3-2357M +- Slotted DIMM 2GiB +- Camera +- pci-e and usb2 on Mini PCI-E slot for wlan +- sata and usb2 on Mini PCI-E slot for wwan +- On board SDHCI connected to pci-e +- libgfxinit-based graphic init +- Sound +- S3 +- EHCI debug +- Seabios Payload + +[flashing tutorial]: ../../flash_tutorial/ext_power.md + diff --git a/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg b/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg new file mode 100644 index 0000000..3fbafce --- /dev/null +++ b/Documentation/mainboard/lenovo/s220_ready_to_flash.jpg Binary files differ diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default index ba33ddf..ad822d5 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.default +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default @@ -2,5 +2,4 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable -volume=0x3 sata_mode=AHCI diff --git a/src/mainboard/lenovo/s220/Kconfig b/src/mainboard/lenovo/s220/Kconfig new file mode 100644 index 0000000..e909399 --- /dev/null +++ b/src/mainboard/lenovo/s220/Kconfig @@ -0,0 +1,59 @@ +if BOARD_LENOVO_THINKPAD_EDGE_S220 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select EC_COMPAL_ENE932 + select EC_ACPI + select NO_UART_ON_SUPERIO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_LVDS + select SERIRQ_CONTINUOUS_MODE + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default lenovo/s220 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad Edge S220/E220s" + +config VGA_BIOS_FILE + string + default "pci8086,0116.rom" + +config VGA_BIOS_ID + string + default "8086,0116" + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config EC_BASE_ADDRESS + hex + default 0xff000000 + +config PS2K_EISAID + default "PTL0001" + +config PS2M_EISAID + default "LEN0031" + +endif diff --git a/src/mainboard/lenovo/s220/Kconfig.name b/src/mainboard/lenovo/s220/Kconfig.name new file mode 100644 index 0000000..78a5af3 --- /dev/null +++ b/src/mainboard/lenovo/s220/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_EDGE_S220 + bool "ThinkPad Edge S220/E220s" diff --git a/src/mainboard/lenovo/s220/Makefile.inc b/src/mainboard/lenovo/s220/Makefile.inc new file mode 100644 index 0000000..a0a3aa1 --- /dev/null +++ b/src/mainboard/lenovo/s220/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += ec.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/s220/acpi/ec.asl b/src/mainboard/lenovo/s220/acpi/ec.asl new file mode 100644 index 0000000..20a9096 --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/ec.asl @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 0) + + Name (_GPE, THINKPAD_EC_GPE) + Mutex (ECLK, 0x07) + + /* EmbeddedControl should work as well, but memory mapped is faster. */ + OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) + Field (ERAM, ByteAcc, Lock, Preserve) + { + , 1, + , 1, + HKFA, 1, // FN lock (Hotkey / FN row toggle) + , 1, + , 1, + , 1, + , 1, + + Offset(0x0c), + HLCL, 8, // LED control + + Offset(0x46), + , 4, + ONAC, 1, + , 3, + + Offset(0x81), + PAGE, 8, + } + + /* Battery info page 0 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xA0), + SBRC, 16, /* Remaining capacity */ + SBFC, 16, /* Full-charge capacity */ + SBAE, 16, + SBRS, 16, + SBAC, 16, /* Present rate */ + SBVO, 16, /* Present voltage */ + SBAF, 16, + SBBS, 16, + } + + /* Battery info page 1 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + , 15, + SBCM, 1, /* Power unit (0 == mA/mAh, 1 == mW/mWh) */ + SBMD, 16, + SBCC, 16, + } + + /* Battery info page 2 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBDC, 16, /* Design Capacity */ + SBDV, 16, /* Design Voltage */ + SBOM, 16, + SBSI, 16, + SBDT, 16, + SBSN, 16, /* Serial number */ + } + + /* Battery info page 4 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBCH, 32, /* Type (LiON) */ + } + + /* Battery info page 5 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBMN, 128, /* Manufacturer */ + } + + /* Battery info page 6 */ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0xA0), + SBDN, 128, /* Model */ + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + IO (Decode16, 0x700, 0x700, 0, 8) + Memory32Fixed(ReadOnly, CONFIG_EC_BASE_ADDRESS, 0x1000, FF00) + }) + Return (ECMD) + } + + /* Increase brightness hotkey */ + Method (_Q14, 0, NotSerialized) { + BRIGHTNESS_UP() + ^HKEY.MHKQ (0x1010) + } + + /* Decrease brightness hotkey */ + Method (_Q15, 0, NotSerialized) { + BRIGHTNESS_DOWN() + ^HKEY.MHKQ (0x1011) + } + + /* Video output switch hotkey */ + Method (_Q16, 0, NotSerialized) { + Notify (\_SB.PCI0.GFX0, 0x82) + ^HKEY.MHKQ (0x1007) + } + + Method (_Q19, 0, NotSerialized) + { + ^HKEY.MHKQ (0x1018) + } + + /* Switched to AC power */ + Method (_Q26, 0, NotSerialized) + { + Store (One, PWRS) + Notify (^AC, 0x80) + Notify (^BAT0, 0x80) + \PNOT () + ^HKEY.MHKQ (0x6040) + } + + /* Switched to battery power */ + Method (_Q27, 0, NotSerialized) + { + Store (Zero, PWRS) + Notify (^AC, 0x80) + Notify (^BAT0, 0x80) + \PNOT () + ^HKEY.MHKQ (0x6040) + } + + /* Lid openend */ + Method (_Q2A, 0, NotSerialized) + { + Store (One, LIDS) + Notify(^LID, 0x80) + ^HKEY.MHKQ (0x5002) + } + + /* Lid closed */ + Method (_Q2B, 0, NotSerialized) + { + Store (Zero, LIDS) + Notify(^LID, 0x80) + ^HKEY.MHKQ (0x5001) + } + + /* Tablet swivel down */ + Method (_Q35, 0, NotSerialized) + { + ^HKEY.MHKQ (0x60c0) + ^HKEY.MHKQ (0x500a) + } + + /* Tablet swivel up */ + Method (_Q36, 0, NotSerialized) + { + ^HKEY.MHKQ (0x60c0) + ^HKEY.MHKQ (0x5009) + } + + /* Tablet rotate lock button */ + Method (_Q37, 0, NotSerialized) + { + ^HKEY.MHKQ (0x6020) + } + + /* Numlock pressed */ + Method (_Q3F, 0, NotSerialized) + { + ^HKEY.MHKQ (0x6000) + } + + /* RFKill status changed */ + Method (_Q41, 0, NotSerialized) { + ^HKEY.MHKQ (0x7000) + } + + /* Mute hotkey */ + Method (_Q43, 0, NotSerialized) { + ^HKEY.MHKQ (0x1017) + } + + /* Settings hotkey */ + Method (_Q5A, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101D) + } + + /* Search hotkey */ + Method (_Q5B, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101E) + } + + /* Scale hotkey */ + Method (_Q5C, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101F) + } + + /* File hotkey */ + Method (_Q5D, 0, NotSerialized) + { + ^HKEY.MHKQ (0x1020) + } + + /* RFkill hotkey */ + Method (_Q64, 0, NotSerialized) { + ^HKEY.MHKQ (0x1005) + } + + /* Mic mute hotkey */ + Method (_Q6A, 0, NotSerialized) + { + ^HKEY.MHKQ (0x101B) + } + + /* FN key pressed */ + Method (_Q70, 0, NotSerialized) { } + + /* FN+Esc pressed / FN row mode switch */ + Method (_Q74, 0, NotSerialized) { + XOr(One, HKFA, HKFA) + ^HKEY.MHKQ (0x6060) + } + + /* Implements enough of the Lenovo hotkey device for + * thinkpad-acpi to work, no real support for hotkey masking */ + Device (HKEY) + { + Name (_HID, EisaId ("LEN0068")) + + Name (DHKC, Zero) + Name (DHKV, Zero) + Name (DHKN, 0xFC018070) // Hotkey mask + Mutex (XDHK, 0x07) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (MHKV, 0, NotSerialized) + { + Return (0x0100) // Interface version 1.0 + } + + Method (MHKA, 0, NotSerialized) // Hotkey all mask + { + Return (0xFFFFFFFF) + } + + Method (MHKM, 2, NotSerialized) // Set hotkey mask + { + Acquire (XDHK, 0xFFFF) + + ShiftLeft (One, Decrement (Arg0), Local0) + If (Arg1) { + Or (Local0, DHKN, DHKN) + } Else { + And (Not(Local0), DHKN, DHKN) + } + + Release (XDHK) + } + + Method (MHKC, 1, NotSerialized) // Hotkey disable? + { + Acquire (XDHK, 0xFFFF) + + Store (Arg0, DHKC) + + Release (XDHK) + } + + Method (MHKP, 0, NotSerialized) // Hotkey poll + { + Acquire (XDHK, 0xFFFF) + + Store (Zero, Local0) + + if (DHKV) { + Store (DHKV, Local0) + Store (Zero, DHKV) + } + + Release (XDHK) + + Return (Local0) + } + + Method (MHKQ, 1, NotSerialized) // Send hotkey event + { + Acquire (XDHK, 0xFFFF) + + Store (Arg0, DHKV) + + Release (XDHK) + + Notify (HKEY, 0x80) // Status Change + } + } + + /* LED support for thinkpad-acpi */ + Method (LED, 2, NotSerialized) + { + Or (Arg0, Arg1, HLCL) + } + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package (1) { \_SB }) + + Method (_PSR, 0, NotSerialized) + { + Return (ONAC) + } + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } + + /* Battery is H8 compatible, but requires an explicit delay */ + #define BATTERY_PAGE_DELAY_MS 20 + #include <ec/lenovo/h8/acpi/battery.asl> + + /* LID is H8 compatible */ + #include <ec/lenovo/h8/acpi/lid.asl> +} diff --git a/src/mainboard/lenovo/s220/acpi/gpe.asl b/src/mainboard/lenovo/s220/acpi/gpe.asl new file mode 100644 index 0000000..8124ec7 --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/gpe.asl @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_GPE) +{ + Name (PDET, Zero) + Method (PNOT, 2, Serialized) { + ShiftLeft (Arg0, Arg1, Local0) + Not( ShiftLeft (One, Arg1), Local1) + Or (Local0, And (Local1, PDET), PDET) + If (LEqual (PDET, Zero)) { + // Palm removed + \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B1) + } Else { + // Palm detected + \_SB.PCI0.LPCB.EC0.HKEY.MHKQ (0x60B0) + } + } + + Method (TINV, 2, Serialized) { + ShiftLeft (One, Arg1, Local0) + If (LEqual (Arg0, Zero)) { + Not (Local0, Local0) + And (GIV0, Local0, GIV0) + } Else { + Or (GIV0, Local0, GIV0) + } + } + + /* Palm detect sensor 1 */ + Method (_L12, 0, NotSerialized) { + // Invert trigger + TINV (GP02, 2) + + PNOT (GP02, 0) + } + + /* Palm detect sensor 2 */ + Method (_L14, 0, NotSerialized) { + // Invert trigger + TINV (GP04, 4) + + PNOT (GP04, 1) + } +} diff --git a/src/mainboard/lenovo/s220/acpi/platform.asl b/src/mainboard/lenovo/s220/acpi/platform.asl new file mode 100644 index 0000000..149fb3a --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/platform.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + /* Turn on radios */ + Store (One, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + Store (One, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + /* There also is RF_OFF# on pin 20, controlled by the EC */ + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* Turn off radios */ + Store (Zero, GP33) /* WLBT_OFF_5# (To pin 5 of WiFi mPCIe) */ + Store (Zero, GP36) /* WLBT_OFF_51# (To pin 51 of WiFi mPCIe) */ + /* There also is RF_OFF# on pin 20, controlled by the EC */ +} + +Scope(\_SI) +{ + Method(_SST, 1, NotSerialized) + { + If (LLess(Arg0, 2)) + { + /* Thinkpad LED on */ + \_SB.PCI0.LPCB.EC0.LED (Zero, 0x80) + } + Else + { + /* Thinkpad LED blinking */ + \_SB.PCI0.LPCB.EC0.LED (Zero, 0xC0) + } + } +} diff --git a/src/mainboard/lenovo/s220/acpi/superio.asl b/src/mainboard/lenovo/s220/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/s220/acpi_tables.c b/src/mainboard/lenovo/s220/acpi_tables.c new file mode 100644 index 0000000..c85058d --- /dev/null +++ b/src/mainboard/lenovo/s220/acpi_tables.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/s220/board_info.txt b/src/mainboard/lenovo/s220/board_info.txt new file mode 100644 index 0000000..cdbf8b8 --- /dev/null +++ b/src/mainboard/lenovo/s220/board_info.txt @@ -0,0 +1,4 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year diff --git a/src/mainboard/lenovo/s220/data.vbt b/src/mainboard/lenovo/s220/data.vbt new file mode 100644 index 0000000..f7882f9 --- /dev/null +++ b/src/mainboard/lenovo/s220/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/s220/devicetree.cb b/src/mainboard/lenovo/s220/devicetree.cb new file mode 100644 index 0000000..22429c9 --- /dev/null +++ b/src/mainboard/lenovo/s220/devicetree.cb @@ -0,0 +1,84 @@ +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_cpu_backlight" = "0x00000f55" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "PANEL_PORT_LVDS" + register "gpu_panel_power_backlight_off_delay" = "2700" + register "gpu_panel_power_backlight_on_delay" = "3800" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "95" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x13121312" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x17aa 0x21e4 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PEG + device pci 02.0 on end # iGPU + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00000000" + register "gen2_dec" = "0x000c0701" + register "gen3_dec" = "0x000c0069" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi7_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x19" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x21e4 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/s220/dsdt.asl b/src/mainboard/lenovo/s220/dsdt.asl new file mode 100644 index 0000000..6d67b91 --- /dev/null +++ b/src/mainboard/lenovo/s220/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 23 + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/gpe.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/s220/early_init.c b/src/mainboard/lenovo/s220/early_init.c new file mode 100644 index 0000000..e04b4df --- /dev/null +++ b/src/mainboard/lenovo/s220/early_init.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 0, 1, 1 }, + { 0, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + /* Memory map KB9012 EC registers */ + pci_write_config32(PCH_LPC_DEV, LGMR, + CONFIG_EC_BASE_ADDRESS | 1); + pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); + + /* Enable external USB port power. */ + if (CONFIG(USBDEBUG)) + ec_mm_set_bit(0x3b, 4); +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/s220/ec.c b/src/mainboard/lenovo/s220/ec.c new file mode 100644 index 0000000..285a8d5 --- /dev/null +++ b/src/mainboard/lenovo/s220/ec.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "ec.h" +#include <ec/compal/ene932/ec.h> + +/* The keyboard matrix tells the EC how the keyboard is wired internally */ +static void set_keyboard_matrix_us(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE5); +} + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */ +static void enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} + +void lenovo_s230u_ec_init(void) +{ + set_keyboard_matrix_us(); + + /* + * The EC has a special "blinking Caps Lock LED" mode which it normally + * enters when it believes the OS is not responding. It occasionally + * disables battery charging when in this mode, although other + * functionality is unaffected. Although the EC starts in APM mode by + * default, it only leaves the "blinking Caps Lock LED" mode after + * receiving the following command. + */ + enter_apm_mode(); + + /* Enable external USB port power. */ + ec_mm_set_bit(0x3b, 4); +} diff --git a/src/mainboard/lenovo/s220/ec.h b/src/mainboard/lenovo/s220/ec.h new file mode 100644 index 0000000..273f58b --- /dev/null +++ b/src/mainboard/lenovo/s220/ec.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _MAINBOARD_LENOVO_S230U_EC_H +#define _MAINBOARD_LENOVO_S230U_EC_H + +void lenovo_s230u_ec_init(void); + +#define ECMM(x) (*((volatile u8 *)(CONFIG_EC_BASE_ADDRESS + x))) +#define ec_mm_read(addr) (ECMM(0x100 + addr)) +#define ec_mm_write(addr, data) (ECMM(0x100 + addr) = data) +#define ec_mm_set_bit(addr, bit) (ECMM(0x100 + addr) |= 1 << bit) +#define ec_mm_clr_bit(addr, bit) (ECMM(0x100 + addr) &= ~(1 << bit)) + +#endif /* _MAINBOARD_LENOVO_S230U_EC_H */ diff --git a/src/mainboard/lenovo/s220/gma-mainboard.ads b/src/mainboard/lenovo/s220/gma-mainboard.ads new file mode 100644 index 0000000..03e6a55 --- /dev/null +++ b/src/mainboard/lenovo/s220/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/s220/gpio.c b/src/mainboard/lenovo/s220/gpio.c new file mode 100644 index 0000000..ea8a906 --- /dev/null +++ b/src/mainboard/lenovo/s220/gpio.c @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_OUTPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/s220/hda_verb.c b/src/mainboard/lenovo/s220/hda_verb.c new file mode 100644 index 0000000..0bb7e02 --- /dev/null +++ b/src/mainboard/lenovo/s220/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x17aa21e4, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x17aa21e4), + AZALIA_PIN_CFG(0, 0x19, 0x04211040), + AZALIA_PIN_CFG(0, 0x1a, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1b, 0x04a11060), + AZALIA_PIN_CFG(0, 0x1c, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x1f, 0x90170110), + AZALIA_PIN_CFG(0, 0x20, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), + AZALIA_PIN_CFG(0, 0x23, 0x90a60170), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x17aa21e4, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x17aa21e4), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/s220/mainboard.c b/src/mainboard/lenovo/s220/mainboard.c new file mode 100644 index 0000000..7f2c7fd --- /dev/null +++ b/src/mainboard/lenovo/s220/mainboard.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <southbridge/intel/common/gpio.h> +#include <string.h> +#include <smbios.h> +#include "ec.h" + +#include <acpi/acpi.h> + +static u8 mainboard_fill_ec_version(char *buf, u8 buf_len) +{ + u8 i, c; + char str[16 + 1]; /* 16 ASCII chars + \0 */ + + /* Build ID */ + for (i = 0; i < 8; i++) { + c = ec_mm_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) { + i = snprintf(str, sizeof(str), "*INVALID"); + break; + } + str[i] = c; + } + + i = MIN(buf_len, i); + memcpy(buf, str, i); + + return i; +} + +static void mainboard_smbios_strings( + struct device *dev, struct smbios_type11 *t) +{ + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + u16 fwvh, fwvl; + + mainboard_fill_ec_version(tpec + 35, 17); + t->count = smbios_add_string(t->eos, tpec); + + /* Apparently byteswapped compared to H8 */ + fwvh = ec_mm_read(0xe8); + fwvl = ec_mm_read(0xe9); + + printk(BIOS_INFO, "EC Firmware ID %.54s, Version %d.%d%d%c\n", tpec, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = mainboard_smbios_strings, + + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); + + if (!acpi_is_wakeup_s3()) + lenovo_s230u_ec_init(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/s220/smihandler.c b/src/mainboard/lenovo/s220/smihandler.c new file mode 100644 index 0000000..62bba44 --- /dev/null +++ b/src/mainboard/lenovo/s220/smihandler.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/compal/ene932/ec.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#include "ec.h" + +#define GPE_PALMDET1 2 +#define GPE_PALMDET2 4 +#define GPE_EC_SCI 7 +#define GPE_EC_SMI 8 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +enum sleep_states { + S0 = 0, + S1 = 1, + S3 = 3, + S4 = 4, + S5 = 5, +}; + +enum ec_smi_event { + EC_SMI_EVENT_IDLE = 0x80, + EC_SMI_BATTERY_LOW = 0xb3, +}; + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs. */ +static void ec_enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} +/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs. */ +static void ec_enter_acpi_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); +} + +static uint8_t ec_get_smi_event(void) +{ + ec_kbc_write_cmd(0x56); + return ec_kbc_read_ob(); +} + +static void ec_process_smi(uint8_t src) +{ + /* + * Reading the SMI source satisfies the EC in terms of responding to + * the event, regardless of whether we take an action or not. + */ + + printk(BIOS_DEBUG, "Unhandled EC_SMI event 0x%x\n", src); +} + +static void handle_ec_smi(void) +{ + uint8_t src; + + while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) + ec_process_smi(src); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SMI)) + handle_ec_smi(); +} + +int mainboard_smi_apmc(u8 data) +{ + printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data); + + switch (data) { + case APM_CNT_ACPI_ENABLE: + printk(BIOS_DEBUG, "Enable ACPI mode\n"); + ec_enter_acpi_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI); + break; + case APM_CNT_ACPI_DISABLE: + printk(BIOS_DEBUG, "Disable ACPI mode\n"); + ec_enter_apm_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + break; + default: + printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == S3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746798b13e83d1971bb7be93751a15875d16c337 Gerrit-Change-Number: 48771 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/*/*{haswell}: Link gpio.c and add a const global for lp variant
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36710 ) Change subject: mb/*/*{haswell}: Link gpio.c and add a const global for lp variant ...................................................................... mb/*/*{haswell}: Link gpio.c and add a const global for lp variant This is similar to how sb/common/intel handles it. The advantage is that the gpio configuration does not need to be passed on that much. Change-Id: I6d07f0d4d3aaf4e8662d6f7dc8238d14a16fd04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/beltino/romstage.c R src/mainboard/google/beltino/variants/mccloud/gpio.c R src/mainboard/google/beltino/variants/monroe/gpio.c R src/mainboard/google/beltino/variants/panther/gpio.c R src/mainboard/google/beltino/variants/tricky/gpio.c R src/mainboard/google/beltino/variants/zako/gpio.c M src/mainboard/google/slippy/Makefile.inc R src/mainboard/google/slippy/variants/falco/gpio.c M src/mainboard/google/slippy/variants/falco/romstage.c R src/mainboard/google/slippy/variants/leon/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c R src/mainboard/google/slippy/variants/peppy/gpio.c M src/mainboard/google/slippy/variants/peppy/romstage.c R src/mainboard/google/slippy/variants/wolf/gpio.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/intel/baskingridge/Makefile.inc R src/mainboard/intel/baskingridge/gpio.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lp_gpio.h M src/southbridge/intel/lynxpoint/pch.h 26 files changed, 25 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36710/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 4c67ba8..7459011 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -134,7 +134,6 @@ struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; - const void *gpio_map; const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *); }; diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 34fd7b0..e28ebf4 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -33,7 +33,7 @@ enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->rcba_config); /* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3deae75..dd4043e 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -92,7 +92,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], }; diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index e1bebc1..7535350 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -21,6 +21,7 @@ smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c romstage-y += variants/$(VARIANT_DIR)/led.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index f206664..5c91bec 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -24,7 +24,6 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include <variant/gpio.h> #include "onboard.h" const struct rcba_config_instruction rcba_config[] = { @@ -128,7 +127,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], }; diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h b/src/mainboard/google/beltino/variants/mccloud/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/mccloud/gpio.c index 116eeeb..47979d2b 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/mccloud/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef MCCLOUD_GPIO_H -#define MCCLOUD_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h b/src/mainboard/google/beltino/variants/monroe/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/monroe/gpio.c index 8423e1e..22ef848 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/monroe/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef MONROE_GPIO_H -#define MONROE_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h b/src/mainboard/google/beltino/variants/panther/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/panther/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/panther/gpio.c index e48f0b4..08142a8 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/panther/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef PANTHER_GPIO_H -#define PANTHER_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/tricky/gpio.c index 6980ebb..df5d333 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/tricky/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef TRICKY_GPIO_H -#define TRICKY_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h b/src/mainboard/google/beltino/variants/zako/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/zako/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/zako/gpio.c index dffefd6..e533bf0 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/zako/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef ZAKO_GPIO_H -#define ZAKO_GPIO_H - +#include <stdint.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 921f9e7..f80dcab 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -21,6 +21,7 @@ smm-y += smihandler.c romstage-y += variants/$(VARIANT_DIR)/romstage.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/falco/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/falco/gpio.c index c35b81e..3fdc032 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/falco/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 1903588..656bf70 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -165,7 +164,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/leon/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/leon/gpio.c index 7527ff2..5ea78f9 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/leon/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef LEON_GPIO_H -#define LEON_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 3ef8eec..2eeb86d 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -24,7 +24,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -160,7 +159,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/peppy/gpio.c index 8eb3da9..00e6a54 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/peppy/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef PEPPY_GPIO_H -#define PEPPY_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 71eafc2..048a154 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../onboard.h" #include "../../variant.h" @@ -177,7 +176,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/wolf/gpio.c index 5c72f73..1dbd5ff 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/wolf/gpio.c @@ -13,10 +13,8 @@ * GNU General Public License for more details. */ -#ifndef WOLF_GPIO_H -#define WOLF_GPIO_H - -struct pch_lp_gpio_map; +#include <stdint.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -116,5 +114,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 7fcf085..cc67c93 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { @@ -164,7 +163,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = copy_spd, }; diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index e34704d..91a7963 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -17,4 +17,6 @@ ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c +romstage-y += gpio.c + smm-y += mainboard_smi.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c similarity index 98% rename from src/mainboard/intel/baskingridge/gpio.h rename to src/mainboard/intel/baskingridge/gpio.c index f2be9e3..3a33f09 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - +#include <stdint.h> #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 1a10931..3d03ab3 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -134,7 +134,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .copy_spd = NULL, }; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 552ebd2..46ec7b2 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -90,7 +90,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .rcba_config = rcba_config, }; diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 25ffdc4..b49d3cf 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -99,17 +99,16 @@ { } -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) +int early_pch_init(const struct rcba_config_instruction *rcba_config) { int wake_from_s3; pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) - setup_pch_lp_gpios(gpio_map); + setup_pch_lp_gpios(mainboard_gpio_map); #else - setup_pch_gpios(gpio_map); + setup_pch_gpios(mainboard_gpio_map); #endif pch_generic_setup(); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 8436243..0464226 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -160,6 +160,8 @@ u8 pirq; } __packed; +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; + /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d83dd17..8802be1 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -181,8 +181,7 @@ #endif void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d07f0d4d3aaf4e8662d6f7dc8238d14a16fd04d Gerrit-Change-Number: 36710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: adding new mainboard (no official website as it is a noname board but...
by Skoll RC (Code Review) 07 Aug '23

07 Aug '23

Skoll RC has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40813 ) Change subject: adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details ...................................................................... adding new mainboard (no official website as it is a noname board but easy to find) see https://github.com/skollrc/coreboot_noname_h61S1_port for more details Signed-off-by: Robin CASSET <amisbievre(a)posteo.net> Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c --- A src/mainboard/ongy/Kconfig A src/mainboard/ongy/Kconfig.name A src/mainboard/ongy/h61m-s1/Kconfig A src/mainboard/ongy/h61m-s1/Kconfig.name A src/mainboard/ongy/h61m-s1/Makefile.inc A src/mainboard/ongy/h61m-s1/acpi/ec.asl A src/mainboard/ongy/h61m-s1/acpi/platform.asl A src/mainboard/ongy/h61m-s1/acpi/superio.asl A src/mainboard/ongy/h61m-s1/acpi_tables.c A src/mainboard/ongy/h61m-s1/board_info.txt A src/mainboard/ongy/h61m-s1/devicetree.cb A src/mainboard/ongy/h61m-s1/dsdt.asl A src/mainboard/ongy/h61m-s1/early_init.c A src/mainboard/ongy/h61m-s1/gma-mainboard.ads A src/mainboard/ongy/h61m-s1/gpio.c A src/mainboard/ongy/h61m-s1/hda_verb.c A src/mainboard/ongy/h61m-s1/mainboard.c 17 files changed, 559 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/40813/1 diff --git a/src/mainboard/ongy/Kconfig b/src/mainboard/ongy/Kconfig new file mode 100644 index 0000000..30ea9f3 --- /dev/null +++ b/src/mainboard/ongy/Kconfig @@ -0,0 +1,14 @@ +if VENDOR_ONGY +choice + prompt "Mainboard model" + +source "src/mainboard/ongy/*/Kconfig.name" + +endchoice + +source "src/mainboard/ongy/*/Kconfig" + +config MAINBOARD_VENDOR + default "H61M-S1" + +endif # VENDOR_ONGY diff --git a/src/mainboard/ongy/Kconfig.name b/src/mainboard/ongy/Kconfig.name new file mode 100644 index 0000000..d0e84b5 --- /dev/null +++ b/src/mainboard/ongy/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ONGY + bool "ongy" diff --git a/src/mainboard/ongy/h61m-s1/Kconfig b/src/mainboard/ongy/h61m-s1/Kconfig new file mode 100644 index 0000000..65bda16 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig @@ -0,0 +1,56 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_H61M_S1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default ongy/h61m-s1 + +config MAINBOARD_PART_NUMBER + string + default "h61m-s1" + +config VGA_BIOS_FILE + string + default "pci8086,0112.rom" + +config VGA_BIOS_ID + string + default "8086,0112" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/ongy/h61m-s1/Kconfig.name b/src/mainboard/ongy/h61m-s1/Kconfig.name new file mode 100644 index 0000000..36eed8c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_H61M_S1 + bool "h61m-s1" diff --git a/src/mainboard/ongy/h61m-s1/Makefile.inc b/src/mainboard/ongy/h61m-s1/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/ongy/h61m-s1/acpi/ec.asl b/src/mainboard/ongy/h61m-s1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/ec.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi/platform.asl b/src/mainboard/ongy/h61m-s1/acpi/platform.asl new file mode 100644 index 0000000..ac9ff88 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/platform.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +/* The _PTS method (Prepare To Sleep) is called before the OS is +* entering a sleep state. The sleep state number is passed in Arg0 +*/ + +Method(_PTS,1) +{ +} + +/*The _WAK method is called on system wakeup*/ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/ongy/h61m-s1/acpi/superio.asl b/src/mainboard/ongy/h61m-s1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi/superio.asl diff --git a/src/mainboard/ongy/h61m-s1/acpi_tables.c b/src/mainboard/ongy/h61m-s1/acpi_tables.c new file mode 100644 index 0000000..3319c25 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/acpi_tables.c @@ -0,0 +1,22 @@ +/* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; +} diff --git a/src/mainboard/ongy/h61m-s1/board_info.txt b/src/mainboard/ongy/h61m-s1/board_info.txt new file mode 100644 index 0000000..0fc073c --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: none +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y \ No newline at end of file diff --git a/src/mainboard/ongy/h61m-s1/devicetree.cb b/src/mainboard/ongy/h61m-s1/devicetree.cb new file mode 100644 index 0000000..38b740f --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/devicetree.cb @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only +## This file is part of the coreboot project. + +chip northbridge/intel/sandybridge + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x1c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x1c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x8086 0x1c20 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x1c10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x8086 0x1c1a + end + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x1c26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x8086 0x1c5c + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x1c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x1c22 + end + device pci 1f.5 off end # SATA Controller 2 + + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x8086 0x0100 + end + device pci 01.0 on # PEG + subsystemid 0x8086 0x0101 + end + device pci 02.0 on # iGPU + subsystemid 0x8086 0x2010 + end + end +end diff --git a/src/mainboard/ongy/h61m-s1/dsdt.asl b/src/mainboard/ongy/h61m-s1/dsdt.asl new file mode 100644 index 0000000..8c67659 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/dsdt.asl @@ -0,0 +1,43 @@ +/* +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/mainboard.asl" + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include "acpi/thermal.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/ongy/h61m-s1/early_init.c b/src/mainboard/ongy/h61m-s1/early_init.c new file mode 100644 index 0000000..6cb36f1 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/early_init.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1401); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/ongy/h61m-s1/gma-mainboard.ads b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads new file mode 100644 index 0000000..e2c84c6 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-only +-- This file is part of the coreboot project. + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/ongy/h61m-s1/gpio.c b/src/mainboard/ongy/h61m-s1/gpio.c new file mode 100644 index 0000000..22f4838 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/gpio.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/ongy/h61m-s1/hda_verb.c b/src/mainboard/ongy/h61m-s1/hda_verb.c new file mode 100644 index 0000000..09748c0 --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/hda_verb.c @@ -0,0 +1,43 @@ +/* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0662, /* Codec Vendor / Device ID: Realtek*/ + 0x10ec0000, /* Subsystem ID*/ + 12, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(2, 0x10ec0000), + AZALIA_PIN_CFG(2, 0x12, 0x40130000), + AZALIA_PIN_CFG(2, 0x14, 0x01014010), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19040), + AZALIA_PIN_CFG(2, 0x19, 0x02a19050), + AZALIA_PIN_CFG(2, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214020), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4044c601), + AZALIA_PIN_CFG(2, 0x1e, 0x01441130), + + 0x80862805, /* Codec Vendor / Device ID: Intel*/ + 0x80860101, /* Subsystem ID*/ + 4, /* Number of 4 dword sets*/ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/ongy/h61m-s1/mainboard.c b/src/mainboard/ongy/h61m-s1/mainboard.c new file mode 100644 index 0000000..3f9c24e --- /dev/null +++ b/src/mainboard/ongy/h61m-s1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/40813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f42ffdbbfb59a1b699ba49650919c1d538c8e6c Gerrit-Change-Number: 40813 Gerrit-PatchSet: 1 Gerrit-Owner: Skoll RC Gerrit-MessageType: newchange

8 115

Change in coreboot[master]: Documentation: Add cache as ram documentation
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36126 ) Change subject: Documentation: Add cache as ram documentation ...................................................................... Documentation: Add cache as ram documentation This add documentation around coreboot's history of CAR usage. The history is reconstructed from articles and git/svn history, but should provide a good overview of the challenges and solutions coreboot came up with to deal with early code execution on X86 platforms. The technical details about CAr will come in follow-up patch and are marked as TODO for now. Change-Id: I964d59a6bd210f3d4d06220d2ec7166110ab2cf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A Documentation/cpu/index.md A Documentation/cpu/x86/car.md M Documentation/index.md 3 files changed, 171 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36126/1 diff --git a/Documentation/cpu/index.md b/Documentation/cpu/index.md new file mode 100644 index 0000000..d9f063f --- /dev/null +++ b/Documentation/cpu/index.md @@ -0,0 +1,5 @@ +# CPU-specific documentation + +This section contains documentation about coreboot on specific CPU. + +* [A gentle introduction to Cache-as-Ram on X86](x86/car.md) diff --git a/Documentation/cpu/x86/car.md b/Documentation/cpu/x86/car.md new file mode 100644 index 0000000..3d2983e --- /dev/null +++ b/Documentation/cpu/x86/car.md @@ -0,0 +1,165 @@ +# A gentle introduction to Cache-as-Ram on X86 + +This explains a bit of history on CAR in coreboot, how it works +and then finally give a more in depth overview at the steps of +how it is set up on Intel CPUs. + +## Glossary + +- Cache-as-RAM/CAR: Using not memory mapped CPU cache as execution + environment. +- XIP: Execute in place on a memory mapped medium +- SRAM: Static Random Access Memory, here: memory mapped memory + that needs no initialization. +- ROMCC: A C compiler using only the CPU registers. + +## Cache-as-Ram, the basics + +When an X86 platforms boot, it starts in a pretty bare environment. +The first instruction is fetched from the top of the boot medium, +which on most x86 platforms is memory mapped below 4G (in 32bit +protected mode). Not only do they start in 16bit 'real' mode, +most of the hardware starts uninitialized. This includes the dram +controller. Another thing about X86 platforms is that they generally +don't feature SRAM, static RAM. SRAM for this purpose of this text is +a small region of ram that is available without any initialization. +Without RAM this leaves the system with just CPU registers and a +memory mapped boot medium of which code can be executed in place (XIP) +to initialize the hardware. + +For simple dram controllers that environment is just fine and +initializing the dram controller in assembly code without using a +stack is very doable. Modern systems however require complex +initialization procedures and writing that in assembly would be either +too hard or simply impossible. To overcome this limitation a technique +called Cache-as-Ram exists. It allows to use the CPU's Cache-as-Ram. +This in turn makes it possible to write the early initialization code +in a higher level programming language compiled by a regular compiler, +e.g. GCC. Typically only the stack is placed in Cache-as-Ram and the +code is still executed in place, but copying code in the cache as ram +and executing from there is also possible. + +For coreboot this means that with only a very small amount of assembly +code to set up CAR, all the other code can written in C, which +compared to writing assembly tremendously increases development speed +and is much less error prone. + +## A bit of history on Cache-as-Ram in coreboot + +### Linux as a BIOS? The invention of romstage + +When LinuxBIOS, later coreboot, started out, the first naive attempt +to run the Linux kernel instead of the legacy BIOS interface, was to +jump straight to loading the kernel. This did not work at all, since +dram was not working at that point. LinuxBIOS v1 therefore +initialized the memory in assembly before it was able to load the +kernel. This executed in place and would later become romstage. It +turned that Linux needed other devices, like enumerated and have it's +resources allocated, so yet another stage, ramstage, was called into +life, but that's another story. + +### coreboot v2: romcc + +In 2003 AMD's K8 CPU's came out. Those CPU's featured an on die memory +controller and also a new point to point BUS for CPU <-> CPU and +CPU <-> IO controller (northbridge) devices. Writing support for +these in assembly became difficult and a better solution was needed. +This is where ROMCC came to the rescue in 2002. ROMCC is a 25K lines +of code C compiler, written by Eric Biederman, that does not use a +stack but uses CPU registers instead. Besides the 8 general purpose +registers on x86 the MMX and SSE registers, respectively _%mm0_-_%mm7_ +and _%xmm0_-_%xmm7_, can be used to store data. ROMCC also converts +all function calls to static inline functions. This has the +disadvantage that a ROMCC compiled stage must be compiled in one go, +linking is not possible. In practice you will see a lot of '#include +_some_file.c_' which is quite unusual in C, because it makes the +inclusion of files fragile. Given that limited amount +'register-stack', it also imposes restrictions on how many levels of +nested function can be achieved. One last issue with ROMCC is that +no-one really dared touching that code, due to its size and complexity +besides its original author. + +Coreboot used ROMCC in the following way: a bootblock written in both +assembly to enter 32bit protected mode would use ROMCC compiled code +to either jump to 'normal/romstage' or 'fallback/romstage' which in +turn was also compiled with romstage. + +### Cache-as-Ram + +While ROMCC was eventually used for early initialization, prior to +that development attempts were made to use the CPU's cache as RAM. +This would allow to use regular GCC compiled and linked code to +be used. The idea is to set up the CPU's cache to Write Back to a +region, while disable cacheline filling or simply hope that no cache +eviction or invalidation happens. Eric Biederman initially got CAR +working, but with the advent of Intel Hyperthreading on the Pentium 4, +on which CAR setup proved to be a little more difficult and he +developed ROMCC instead. + +Around 2006 a lot was learned from coreboot v2 with its ROMCC usage +and development on coreboot v3 was started. The decision was mode to +not use ROMCC anymore and use Cache Memory for early stages. The +results were good as init object code size is reduced by factor of +four. So the code was smaller and faster at the same time. + +coreboot v4 sort of merged v2 and v3, so it was a mix of ROMCC compiled +romstage and romstage with CAR. + +In 2014 Support for ROMCC compiled romstage was dropped. + +### Intel Apollolake, a new era: POSTCAR_STAGE and C_ENVIRONMENT_BOOTBLOCK + +In 2016 Intel released the ApolloLake architecture. This architecture +is a weird duck in the X86 pool. It is the first Intel CPU to feature +MMC as a boot medium and does not memory map it. It also features to +the main CPU read only SRAM that is mapped right below 4G. The +bootblock is copied to SRAM and executed. Given that the boot medium +is not always memory mapped XIP is not an option. The solution is to +set up CAR in the bootblock and copy the romstage in CAR. We call this +C_ENVIRONMENT_BOOTBLOCK, because it runs GCC compiled code. Granted +XIP is still possible on ApolloLake, but coreboot has to use Intel's +blob, FSP-M, and it is linked to run in CAR, so a blob actually forced +a nice feature in coreboot! + +Another issue arises with this setup. With romstage running from the +read only boot medium, you can continue executing code (albeit without +stack) to tear down the CAR and start executing code from 'real' RAM. +On ApolloLake with romstage executing from CAR, tearing down CAR in +there, would shooting in ones own foot, as our code would be gone +in doing so. The solution was to tear down CAR in a separate stage, +named 'postcar' stage. This provides a clean separation of programs +and results in needing less linker scripts hacks in romstage. This +solution was therefore adopted by many other platforms that still did +XIP. + +### AMD Zen, 2019 + +On AMD Zen the first CPU to come out of reset is the PSP and it +initializes the dram before pulling out the main CPU out of reset. +CAR won't be needed, nor used on this platform. + +### The future? + +For coreboot release 4.11, scheduled for october 2019, support for +ROMCC in the bootblock will be dropped as will support for the messy +tearing down of CAR in romstage as opposed to doing that in a separate +stage. + +## In depth analysis + +### CAR setup + +TODO: MTRR, IPI/hyperthreaded, ROM Caching, Non-evict + +### Linker symbols + +TODO: sharing things over multiple CAR stages: car.ld + +### CAR teardown + +TODO: postcarstage, NO_CAR_GLOBAL_MIGRATION + +## References +[2007, The Open Source BIOS is Ten An interview with the coreboot developers](http://www.h-online.com/open/features/The-Open-Source-BIOS-is-T… +[A Framework for Using Processor Cache-as-Ram (CAR)](https://www.coreboot.org/images/6/6c/LBCar.pdf) +[CAR: Using Cache-as-Ram in LinuxBIOS](https://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.pdf) diff --git a/Documentation/index.md b/Documentation/index.md index 1c04ad3..85666cb 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -177,6 +177,7 @@ * [Display panel-specific documentation](gfx/display-panel.md) * [Architecture-specific documentation](arch/index.md) * [Platform independend drivers documentation](drivers/index.md) +* [CPU-specific documentation](cpu/index.md) * [Northbridge-specific documentation](northbridge/index.md) * [System on Chip-specific documentation](soc/index.md) * [Mainboard-specific documentation](mainboard/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/36126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964d59a6bd210f3d4d06220d2ec7166110ab2cf3 Gerrit-Change-Number: 36126 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/skylake: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 07 Aug '23

07 Aug '23

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42213 ) Change subject: soc/intel/skylake: Add romstage common stage file ...................................................................... soc/intel/skylake: Add romstage common stage file Change-Id: I31dc5baca23c3d339fbe5fb06b8049789d9ba415 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/include/soc/romstage.h M src/soc/intel/skylake/romstage/Makefile.inc D src/soc/intel/skylake/romstage/pch.c M src/soc/intel/skylake/romstage/romstage.c 6 files changed, 13 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42213/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 27c1084..c7b61bd 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -81,6 +81,8 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING + select SOC_INTEL_COMMON_BASECODE + select SOC_INTEL_COMMON_BASECODE_ROMSTAGE config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 75121ab..ee81567 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -106,6 +106,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include # Currently used for microcode path. CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index b9eea98..cb11f50 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -7,7 +7,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void romstage_pch_init(void); int smbus_read_byte(unsigned int device, unsigned int address); /* Board type */ enum board_type { diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 1b069b6..dff89ce 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,3 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c -romstage-y += pch.c diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c deleted file mode 100644 index c85bdd6..0000000 --- a/src/soc/intel/skylake/romstage/pch.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <intelblocks/smbus.h> -#include <intelblocks/tco.h> -#include <soc/romstage.h> - -void romstage_pch_init(void) -{ - /* Program TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and enable it */ - smbus_common_init(); -} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 99f444a..c709cf8 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -21,6 +21,7 @@ #include <soc/systemagent.h> #include <string.h> #include <security/vboot/vboot_common.h> +#include <intelbasecode/romstage.h> #include "../chip.h" @@ -37,6 +38,8 @@ CHANNEL_PRESENT }; +void romstage_cpu_init(void) {/*Stub function*/} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -126,20 +129,10 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void mainboard_romstage_entry(void) +void romstage_soc_post_mem_init(void) { - bool s3wake; - struct chipset_power_state *ps; - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* Program PCH init */ - romstage_pch_init(); - ps = pmc_get_power_state(); - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!romstage_is_s3wake()) save_dimm_info(); } @@ -269,7 +262,7 @@ m_cfg->PrimaryDisplay = config->PrimaryDisplay; } -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +void romstage_soc_mem_init_params(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_skylake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -303,6 +296,10 @@ soc_primary_gfx_config_params(m_cfg, config); m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; +} + +void romstage_mb_mem_init_params(FSPM_UPD *mupd) +{ mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31dc5baca23c3d339fbe5fb06b8049789d9ba415 Gerrit-Change-Number: 42213 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/cannonlake: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 07 Aug '23

07 Aug '23

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37883 ) Change subject: soc/intel/cannonlake: Add romstage common stage file ...................................................................... soc/intel/cannonlake: Add romstage common stage file Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/romstage/romstage.c 3 files changed, 124 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37883/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c744e99..16bcad6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -113,6 +113,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include # DSP firmware settings files. NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5c74d4a..9adae3d 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -27,109 +27,6 @@ #include "../chip.h" -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) -{ - unsigned int i; - uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); - - /* Set IGD stolen size to 64MB. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->SaGv = config->SaGv; - if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) - m_cfg->UserBd = BOARD_TYPE_DESKTOP; - else - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->RMT; - - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); - m_cfg->EnableC6Dram = config->enable_c6dram; -#if CONFIG(SOC_INTEL_COMETLAKE) - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; -#else - m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; -#endif - /* - * PcdDebugInterfaceFlags - * This config will allow coreboot to pass information to the FSP - * regarding which debug interface is being used. - * Debug Interfaces: - * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub - * BIT2 - Not used. - */ - m_cfg->PcdDebugInterfaceFlags = - CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; - - /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ - m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - -#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; -#endif - - if (config->cpu_ratio_override) { - m_cfg->CpuRatio = config->cpu_ratio_override; - } else { - /* Set CpuRatio to match existing MSR value */ - msr_t flex_ratio; - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; - } - - /* If ISH is enabled, enable ISH elements */ - if (!dev) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = dev->enabled; - - /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; - - /* Enable IPU only if the device is enabled */ - m_cfg->SaIpuEnable = 0; - dev = pcidev_path_on_root(SA_DEVFN_IPU); - if (dev) - m_cfg->SaIpuEnable = dev->enabled; -} - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); - assert(dev != NULL); - const config_t *config = config_of(dev); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; - - soc_memory_init_params(m_cfg, config); - - /* Enable SMBus controller based on config */ - if (!smbus) - m_cfg->SmbusEnable = 0; - else - m_cfg->SmbusEnable = smbus->enabled; - - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = - CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; - - /* Configure VT-d */ - tconfig->VtdDisable = 0; - - mainboard_memory_init_params(mupd); -} - __weak void mainboard_memory_init_params(FSPM_UPD *mupd) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index f782f63..668ca50 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -27,6 +27,11 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <string.h> +#include <intelbasecode/romstage.h> +#include <assert.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/msr.h> +#include <cpu/x86/msr.h> #include "../chip.h" @@ -41,6 +46,121 @@ /* Default weak implementation, no need to override part number. */ } +void cnlk_soc_post_mem_init(void); + +void cnlk_soc_mem_init_params(FSPM_UPD *mupd); + +static struct romstage_ops cnlk_rs_ops = { + &romstage_cmn_soc_init, + &romstage_cmn_pch_init, + &romstage_cmn_cpu_init, + &romstage_cmn_is_s3wake, + &romstage_cmn_soc_mem_init_param, + &mainboard_memory_init_params, + &cnlk_soc_post_mem_init, + &cnlk_soc_post_mem_init +}; + +struct romstage_ops *soc_get_ops(void) +{ + return &cnlk_rs_ops; +} + +void cnlk_soc_mem_init_params(FSPM_UPD *mupd) +{ + unsigned int i; + uint32_t mask = 0; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const config_t *config = config_of(dev); + + assert(dev != NULL); + config = config_of(dev); + dev = pcidev_path_on_root(PCH_DEVFN_ISH); + /* Set IGD stolen size to 64MB. */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + m_cfg->UserBd = BOARD_TYPE_DESKTOP; + else + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else + m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif + /* + * PcdDebugInterfaceFlags + * This config will allow coreboot to pass information to the FSP + * regarding which debug interface is being used. + * Debug Interfaces: + * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub + * BIT2 - Not used. + */ + m_cfg->PcdDebugInterfaceFlags = + CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + +#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS) + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; +#endif + + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } + + /* If ISH is enabled, enable ISH elements */ + if (!dev) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = dev->enabled; + + /* If HDA is enabled, enable HDA elements */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + /* Enable IPU only if the device is enabled */ + m_cfg->SaIpuEnable = 0; + dev = pcidev_path_on_root(SA_DEVFN_IPU); + if (dev) + m_cfg->SaIpuEnable = dev->enabled; + + /* Enable SMBus controller based on config */ + dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); + if (!dev) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = dev->enabled; + + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = + CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; + + /* Configure VT-d */ + mupd->FspmTestConfig.VtdDisable = 0; +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { @@ -125,19 +245,10 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void mainboard_romstage_entry(void) +void cnlk_soc_post_mem_init(void) { - bool s3wake; - struct chipset_power_state *ps = pmc_get_power_state(); - - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ - systemagent_early_init(); - /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); - - s3wake = pmc_fill_power_state(ps) == ACPI_S3; - fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!cnlk_rs_ops.is_s3wake()) save_dimm_info(); } + -- To view, visit https://review.coreboot.org/c/coreboot/+/37883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I480bd720708496e393cdc7e85876a2209fe639fc Gerrit-Change-Number: 37883 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: Apple Mac Mini (mid 2011)
by Mac Mini (Code Review) 07 Aug '23

07 Aug '23

Mac Mini has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49074 ) Change subject: Apple Mac Mini (mid 2011) ...................................................................... Apple Mac Mini (mid 2011) Autoported and tested on real device Signed-off-by: Mac Mini <mac-mini-2011(a)outlook.com> Change-Id: Ied578e8a9c7ff2c041b5495491acb256019f1c6d --- A src/mainboard/apple/macmini5_1/Kconfig A src/mainboard/apple/macmini5_1/Kconfig.name A src/mainboard/apple/macmini5_1/Makefile.inc A src/mainboard/apple/macmini5_1/acpi/ec.asl A src/mainboard/apple/macmini5_1/acpi/platform.asl A src/mainboard/apple/macmini5_1/acpi/superio.asl A src/mainboard/apple/macmini5_1/acpi_tables.c A src/mainboard/apple/macmini5_1/board_info.txt A src/mainboard/apple/macmini5_1/devicetree.cb A src/mainboard/apple/macmini5_1/dsdt.asl A src/mainboard/apple/macmini5_1/early_init.c A src/mainboard/apple/macmini5_1/gma-mainboard.ads A src/mainboard/apple/macmini5_1/gpio.c A src/mainboard/apple/macmini5_1/hda_verb.c A src/mainboard/apple/macmini5_1/mainboard.c 15 files changed, 494 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49074/1 diff --git a/src/mainboard/apple/macmini5_1/Kconfig b/src/mainboard/apple/macmini5_1/Kconfig new file mode 100644 index 0000000..edc994e --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Kconfig @@ -0,0 +1,36 @@ +if BOARD_APPLE_MACMINI5_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select MAINBOARD_HAS_LIBGFXINIT + # select HAVE_CMOS_DEFAULT + # select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default "apple/macmini5_1" + +config MAINBOARD_PART_NUMBER + string + default "Macmini5,1" + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO + int + default 30 +endif diff --git a/src/mainboard/apple/macmini5_1/Kconfig.name b/src/mainboard/apple/macmini5_1/Kconfig.name new file mode 100644 index 0000000..bca6a27 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACMINI5_1 + bool "Macmini5,1" diff --git a/src/mainboard/apple/macmini5_1/Makefile.inc b/src/mainboard/apple/macmini5_1/Makefile.inc new file mode 100644 index 0000000..e402ffa --- /dev/null +++ b/src/mainboard/apple/macmini5_1/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macmini5_1/acpi/ec.asl b/src/mainboard/apple/macmini5_1/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/ec.asl diff --git a/src/mainboard/apple/macmini5_1/acpi/platform.asl b/src/mainboard/apple/macmini5_1/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/apple/macmini5_1/acpi/superio.asl b/src/mainboard/apple/macmini5_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi/superio.asl diff --git a/src/mainboard/apple/macmini5_1/acpi_tables.c b/src/mainboard/apple/macmini5_1/acpi_tables.c new file mode 100644 index 0000000..161689d --- /dev/null +++ b/src/mainboard/apple/macmini5_1/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macmini5_1/board_info.txt b/src/mainboard/apple/macmini5_1/board_info.txt new file mode 100644 index 0000000..85a3d5d --- /dev/null +++ b/src/mainboard/apple/macmini5_1/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM protocol: SPI +Flashrom support: y +ROM package: SOIC-8 +ROM socketed: n +Release year: 2011 diff --git a/src/mainboard/apple/macmini5_1/devicetree.cb b/src/mainboard/apple/macmini5_1/devicetree.cb new file mode 100644 index 0000000..820bba9 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/devicetree.cb @@ -0,0 +1,77 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x8086 0x7270 inherit + + device pci 00.0 on # Host bridge + subsystemid 0x106b 0x00e6 + end + device pci 01.0 on # PCI Express Graphics + subsystemid 0x106b 0x00e6 + end + device pci 01.1 on # Thunderbolt + subsystemid 0x106b 0x00e6 + end + device pci 02.0 on # iGPU + subsystemid 0x106b 0x00e6 + end + device pci 04.0 off end # Signal Processing Controller ?? + + chip southbridge/intel/bd82x6x # Intel Series 6 Chipset + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1a.7 on end + + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # Ethernet Controller + device pci 1c.1 on end # Broadcom WiFi + device pci 1c.2 on end # FireWire + + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1d.7 on end + + device pci 1e.0 off end # PCI bridge + + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macmini5_1/dsdt.asl b/src/mainboard/apple/macmini5_1/dsdt.asl new file mode 100644 index 0000000..27d14ae --- /dev/null +++ b/src/mainboard/apple/macmini5_1/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/apple/macmini5_1/early_init.c b/src/mainboard/apple/macmini5_1/early_init.c new file mode 100644 index 0000000..c02d482 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/early_init.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/apple/macmini5_1/gma-mainboard.ads b/src/mainboard/apple/macmini5_1/gma-mainboard.ads new file mode 100644 index 0000000..e07e1e9 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP1, HDMI1, DP3, HDMI3, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macmini5_1/gpio.c b/src/mainboard/apple/macmini5_1/gpio.c new file mode 100644 index 0000000..e69fd26 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macmini5_1/hda_verb.c b/src/mainboard/apple/macmini5_1/hda_verb.c new file mode 100644 index 0000000..e622098 --- /dev/null +++ b/src/mainboard/apple/macmini5_1/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2100, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x106b2100), + AZALIA_PIN_CFG(0, 0x09, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0a, 0x002b4040), + AZALIA_PIN_CFG(0, 0x0b, 0x90100130), + AZALIA_PIN_CFG(0, 0x0c, 0x008b3010), + AZALIA_PIN_CFG(0, 0x0d, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0e, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x00cbe020), + AZALIA_PIN_CFG(0, 0x10, 0x004be050), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560010), + AZALIA_PIN_CFG(3, 0x07, 0x18560010), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macmini5_1/mainboard.c b/src/mainboard/apple/macmini5_1/mainboard.c new file mode 100644 index 0000000..e90d85e --- /dev/null +++ b/src/mainboard/apple/macmini5_1/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler( + GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, + 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/49074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied578e8a9c7ff2c041b5495491acb256019f1c6d Gerrit-Change-Number: 49074 Gerrit-PatchSet: 1 Gerrit-Owner: Mac Mini <mac-mini-2011(a)outlook.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022