coreboot-gerrit November 2022

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[M] Change in coreboot[master]: libpayload: Enable LTO by default
by Paul Menzel (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Nico Huber, Stefan Reinauer, Paul Menzel, Julius Werner. Hello build bot (Jenkins), Nico Huber, Angel Pons, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51177 to look at the new patch set (#13). Change subject: libpayload: Enable LTO by default ...................................................................... libpayload: Enable LTO by default Link Time Optimization (LTO) decreases the size of the binaries, which is important for firmware with small flash ROM chip sizes. Using LTO might result in longer build times, which is not an issue for a small project like libpayload. Therefore, enable LTO by default. TEST=Build coreinfo without and with LTO and test with emulation/qemu-i440fx. qemu-system-x86_64 -bios coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda /dev/shm/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22 ``` $ make -j4 # no LTO […] LPGCC coreinfo.bin /usr/bin/ld.bfd: warning: exception_asm.libc.o: missing .note.GNU-stack section implies executable stack /usr/bin/ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker /usr/bin/ld.bfd: warning: build/coreinfo.bin has a LOAD segment with RWX permissions DEBUG coreinfo.debug STRIP coreinfo.elf real 0m9,101s user 0m8,754s sys 0m1,526s $ ls -ltra build/coreinfo.{bin,debug,elf} -rwxr-xr-x 1 user user 648248 10. Nov 19:00 build/coreinfo.bin -rwxr-xr-x 1 user user 545704 10. Nov 19:00 build/coreinfo.debug -rwxr-xr-x 1 user user 130788 10. Nov 19:00 build/coreinfo.elf ``` ``` $ make -j4 # with LTO […] LPGCC coreinfo.bin lto-wrapper: warning: using serial compilation of 2 LTRANS jobs lto-wrapper: note: see the '-flto' option documentation for more information /usr/bin/ld.bfd: warning: exception_asm.libc.o: missing .note.GNU-stack section implies executable stack /usr/bin/ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker /usr/bin/ld.bfd: warning: build/coreinfo.bin has a LOAD segment with RWX permissions DEBUG coreinfo.debug STRIP coreinfo.elf real 0m6,675s user 0m6,399s sys 0m1,395s $ ls -ltra build/coreinfo.{bin,debug,elf} -rwxr-xr-x 1 user user 616612 10. Nov 19:01 build/coreinfo.bin -rwxr-xr-x 1 user user 518340 10. Nov 19:01 build/coreinfo.debug -rwxr-xr-x 1 user user 125988 10. Nov 19:01 build/coreinfo.elf ``` So real time usage actually decreased by 33 % from nine to six seconds, and size of the ELF by 4 % from 130.8 to 126.0 bytes Change-Id: I4bc58034ea8a9510ddc08d61d19e75a7c6f9cbc7 Signed-off-by: Paul Menzel <user(a)molgen.mpg.de> --- M payloads/libpayload/Kconfig 1 file changed, 66 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/51177/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/51177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc58034ea8a9510ddc08d61d19e75a7c6f9cbc7 Gerrit-Change-Number: 51177 Gerrit-PatchSet: 13 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69507 ) Change subject: soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion ...................................................................... soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion Explicitly cast integers to fix building for long mode. Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/psp_smm_gen2.c 1 file changed, 18 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/psp_smm_gen2.c b/src/soc/amd/common/block/psp/psp_smm_gen2.c index f02723a..6bf079d5 100644 --- a/src/soc/amd/common/block/psp/psp_smm_gen2.c +++ b/src/soc/amd/common/block/psp/psp_smm_gen2.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/psp.h> #include <amdblocks/smi.h> +#include <stdint.h> void soc_fill_smm_trig_info(struct smm_trigger_info *trig) { @@ -13,8 +14,8 @@ trig->address = (uintptr_t)acpimmio_smi + SMI_REG_SMITRIG0; trig->address_type = SMM_TRIGGER_MEM; trig->value_width = SMM_TRIGGER_DWORD; - trig->value_and_mask = ~SMITRIG0_PSP; - trig->value_or_mask = SMITRIG0_PSP; + trig->value_and_mask = (uint32_t)~SMITRIG0_PSP; + trig->value_or_mask = (uint32_t)SMITRIG0_PSP; } void soc_fill_smm_reg_info(struct smm_register_info *reg) -- To view, visit https://review.coreboot.org/c/coreboot/+/69507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e Gerrit-Change-Number: 69507 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree
by Felix Held (Code Review) 15 Nov '22

15 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69290 ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree ...................................................................... nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/northbridge.c 4 files changed, 21 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 63f4af2..4631b8e 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -18,12 +18,14 @@ register "gpu_pch_backlight" = "0x061a061a" device cpu_cluster 0 on + ops ironlake_cpu_bus_ops chip cpu/intel/model_2065x device lapic 0 on end end end device domain 0 on + ops ironlake_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 end diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index effe4ef..73b0437 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -19,12 +19,14 @@ register "gpu_pch_backlight" = "0x061a061a" device cpu_cluster 0 on + ops ironlake_cpu_bus_ops chip cpu/intel/model_2065x device lapic 0 on end end end device domain 0 on + ops ironlake_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 end diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 57d2dd7..b49f4d5 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -19,12 +19,14 @@ register "gpu_pch_backlight" = "0x061a061a" device cpu_cluster 0 on + ops ironlake_cpu_bus_ops chip cpu/intel/model_2065x device lapic 0 on end end end device domain 0 on + ops ironlake_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 end diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index fbad6d4..4935ea9 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -75,7 +75,7 @@ } #endif -static struct device_operations pci_domain_ops = { +struct device_operations ironlake_pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, @@ -217,24 +217,13 @@ .devices = pci_device_ids, }; -static struct device_operations cpu_bus_ops = { +struct device_operations ironlake_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_intel_ironlake_ops = { CHIP_NAME("Intel Ironlake integrated Northbridge") - .enable_dev = enable_dev, .init = ironlake_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f Gerrit-Change-Number: 69290 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: security/tpm: make tis_probe() return tpm_family
by Sergii Dmytruk (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69159 ) Change subject: security/tpm: make tis_probe() return tpm_family ...................................................................... Patch Set 4: (1 comment) File src/drivers/i2c/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/69159/comment/b0bc58bd_bef5a0c8 PS1, Line 461: *tpm_family = 1; > OK, now I'm confused. […] Judging by the differences in addresses they might have implemented their own protocol derived from SPI before there was one for I2C interface. They do use constants from `tis.h` for STS register, so maybe family information is there, but no guarantee for that. -- To view, visit https://review.coreboot.org/c/coreboot/+/69159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Gerrit-Change-Number: 69159 Gerrit-PatchSet: 4 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 22:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] soc/amd: Use ioapic helper functions
by Felix Held (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Kyösti Mälkki, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55571 ) Change subject: [WIP] soc/amd: Use ioapic helper functions ...................................................................... Patch Set 10: Code-Review+1 (2 comments) Patchset: PS1: > it looks like that that info was only needed for generating the IVRS table back when it was generate […] i'm not sure if fsp still uses the ioapic IDs; asked about this in an internal chat. in the current setup with an fch ioapic and a nb ioapic with the fch one always being number 0, we'll end up with the correct IDs Patchset: PS10: reviewed the code and ran a test on amd/mandolin and everything works and linux shows me the expected ioapic configuration in dmesg -- To view, visit https://review.coreboot.org/c/coreboot/+/55571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Gerrit-Change-Number: 55571 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 21:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: add log level parameter to fsp_print_guid
by Felix Held (Code Review) 14 Nov '22

14 Nov '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69599 ) Change subject: drivers/intel/fsp2_0: add log level parameter to fsp_print_guid ...................................................................... drivers/intel/fsp2_0: add log level parameter to fsp_print_guid Not all functions that call fsp_print_guid print their output with the BIOS_SPEW log level, so introduce a new log level parameter so that the caller of fsp_print_guid can specify which log level fsp_print_guid should use for printing the GUID. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d --- M src/drivers/intel/fsp2_0/fsp_timestamp.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/include/fsp/debug.h M src/soc/intel/xeon_sp/skx/hob_display.c 5 files changed, 24 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/69599/1 diff --git a/src/drivers/intel/fsp2_0/fsp_timestamp.c b/src/drivers/intel/fsp2_0/fsp_timestamp.c index da14db9..d3f5026 100644 --- a/src/drivers/intel/fsp2_0/fsp_timestamp.c +++ b/src/drivers/intel/fsp2_0/fsp_timestamp.c @@ -46,7 +46,7 @@ static void print_guid_record(const struct generic_event_record *rec) { printk(BIOS_INFO, "%5x\t%16llu\t\t", rec->progress_id, TIMESTAMP_MS(rec->timestamp)); - fsp_print_guid(rec->guid); + fsp_print_guid(BIOS_INFO, rec->guid); printk(BIOS_INFO, "\n"); } @@ -55,7 +55,7 @@ size_t str_len = rec->header.length - offsetof(struct generic_event_record, string); printk(BIOS_INFO, "%5x\t%16llu\t\t%*s/", rec->progress_id, TIMESTAMP_MS(rec->timestamp), (int)str_len, rec->string); - fsp_print_guid(rec->guid); + fsp_print_guid(BIOS_INFO, rec->guid); printk(BIOS_INFO, "\n"); } diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 2ded33699..f0f580b 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -190,7 +190,7 @@ return CB_ERR; } -void fsp_print_guid(const void *base) +void fsp_print_guid(int level, const void *base) { uint32_t big; uint16_t mid[2]; @@ -200,7 +200,7 @@ mid[0] = read16(id + 4); mid[1] = read16(id + 6); - printk(BIOS_SPEW, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + printk(level, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", big, mid[0], mid[1], id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } @@ -216,7 +216,7 @@ range_entry_init(re, 0, 0, 0); if (fsp_hob_iterator_get_next_guid_resource(&hob_iterator, guid, &fsp_mem) != CB_SUCCESS) { - fsp_print_guid(guid); + fsp_print_guid(BIOS_SPEW, guid); printk(BIOS_SPEW, " not found!\n"); return -1; } diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index f21ebfe..9340663 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -97,7 +97,7 @@ printk(BIOS_SPEW, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); if (!fsp_guid_compare(res->owner_guid, empty_guid)) { printk(BIOS_SPEW, "\tOwner GUID: "); - fsp_print_guid(res->owner_guid); + fsp_print_guid(BIOS_SPEW, res->owner_guid); printk(BIOS_SPEW, " (%s)\n", fsp_get_guid_name(res->owner_guid)); } @@ -159,7 +159,7 @@ res = fsp_hob_header_to_resource(hob); printk(BIOS_SPEW, "\t"); - fsp_print_guid(res->owner_guid); + fsp_print_guid(BIOS_SPEW, res->owner_guid); printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid)); /* Some of the SoC FSP specific hobs are of type HOB_TYPE_GUID_EXTENSION */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index b6f982a..044ce95 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -51,7 +51,7 @@ /* FSP debug utility functions */ void fsp_display_upd_value(const char *name, size_t size, uint64_t old, uint64_t new); -void fsp_print_guid(const void *guid); +void fsp_print_guid(int level, const void *guid); void fsp_print_memory_resource_hobs(void); void fsp_print_resource_descriptor(const void *base); const char *fsp_get_hob_type_name(const struct hob_header *hob); diff --git a/src/soc/intel/xeon_sp/skx/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c index efe1038..9c03146 100644 --- a/src/soc/intel/xeon_sp/skx/hob_display.c +++ b/src/soc/intel/xeon_sp/skx/hob_display.c @@ -41,7 +41,7 @@ printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n", res->type, res->attribute_type, res->addr, res->length); printk(BIOS_DEBUG, "\tOwner GUID: "); - fsp_print_guid(res->owner_guid); + fsp_print_guid(BIOS_DEBUG, res->owner_guid); printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid)); if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/69599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d Gerrit-Change-Number: 69599 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/amd/gardenia,pademelon: rewrite IRQ mapping handling
by Martin Roth (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68852 ) Change subject: mb/amd/gardenia,pademelon: rewrite IRQ mapping handling ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia460b467990be7c3e6261440505988a9770ea084 Gerrit-Change-Number: 68852 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Nov 2022 20:21:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/kahlee/mainboard: rewrite IRQ mapping handling
by Martin Roth (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Jason Nien, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68851 ) Change subject: mb/google/kahlee/mainboard: rewrite IRQ mapping handling ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 Gerrit-Change-Number: 68851 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Nov 2022 20:20:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Create crystaldrift variant
by Paul Fagerburg (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Chao Gui, Jason Nien, Isaac Lee, Jon Murphy, Martin Roth, Karthik Ramasubramanian. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69479 ) Change subject: mb/google/skyrim: Create crystaldrift variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb3ebaa7e4af1a03173b93b8c4fbd342f7cd7100 Gerrit-Change-Number: 69479 Gerrit-PatchSet: 1 Gerrit-Owner: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-CC: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Attention: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 19:50:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] drivers/intel/fsp2_0/hand_off_block: limit number of processed ...
by Felix Held (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Andrey Petrov. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69580 ) Change subject: [RFC] drivers/intel/fsp2_0/hand_off_block: limit number of processed HOBs ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/69580/comment/240f1e17_a9ee52fc PS1, Line 156: "further HOBs. There's likely somthing wrong with the HOB data " fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/69580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie89c5b7e0aff7926e819aca455554370afd36f43 Gerrit-Change-Number: 69580 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 19:28:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2022