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Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/me.c:
https://review.coreboot.org/c/coreboot/+/69324/comment/6e21df37_c82a1fd7
PS1, Line 141: hfsts1.fields.mfg_mode
> Marking this resolved. Feel free to reopen.
+1 to Reka comments.
>what Manufacturing Mode we want to report here?
It is same like earlier, but starting from TGL platform, Intel has given options to indicate the status of SPI protection, Fuses programmed n manufacturing variables locked to support the flexible EOM where in manufacturing can be done in 2 stages.
These pre-requisites must be met by the production system.
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
Patch Set 22:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/5c8bf713_91ca16be
PS16, Line 393: #else
> > Since many default and low/now battery entries duplicated, do we need to expand the parameters for […]
I will keep the current design and fill out src/mainboard/google/skyrim/variants/skyrim/overridetree.cb with any missing values as below.
config->vrm_current_limit_throttle_mA,
config->vrm_maximum_current_limit_throttle_mA,
config->vrm_soc_current_limit_throttle_mA,
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Change subject: Makefile.inc: Remove workaround ACPI warnings
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Patch Set 3: Code-Review+2
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Change subject: mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VD
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Patch Set 3:
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Change subject: cbmem_top_chipset: Change the return value to uintptr_t
......................................................................
Patch Set 11:
(1 comment)
File src/soc/qualcomm/qcs405/cbmem.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/e1386466_ebe76005
PS10, Line 7: (uintptr_t)
> without (uintptr_t), it complains: […]
Oh. So cast has to stay. Good to know. Please, put it back.
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Change subject: cbmem_top_chipset: Change the return value to uintptr_t
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Patch Set 11:
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File src/soc/qualcomm/qcs405/cbmem.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/178af6be_00ec4db4
PS10, Line 7: (uintptr_t)
> Done
without (uintptr_t), it complains:
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https://qa.coreboot.org/job/coreboot-gerrit/222216/#showFailuresLink
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Change subject: soc/amd/common/acpi: Implement DTTS Proposal
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Patch Set 44:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/68471/comment/98c73974_e38f4e47
PS41, Line 7: common/acpi/dptc: Implement DTTS Proposal
> soc/amd/common/acpi:
Done
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Change subject: soc/amd/common/acpi: Implement DTTS Proposal
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Patch Set 44:
(5 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163691):
https://review.coreboot.org/c/coreboot/+/68471/comment/07b4a973_50bbb02f
PS44, Line 13:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163691):
https://review.coreboot.org/c/coreboot/+/68471/comment/9393fa9e_43160c7c
PS44, Line 39: switch to C with Lid close event, if temperature is over 55C, EC will
Possible unwrapped commit description (prefer a maximum 72 chars per line)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163691):
https://review.coreboot.org/c/coreboot/+/68471/comment/72e7af8e_fb7fb379
PS44, Line 40: trigger temperature to switch form table C to D.
Possible unwrapped commit description (prefer a maximum 72 chars per line)
File src/soc/amd/common/acpi/DTTS.asl:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163691):
https://review.coreboot.org/c/coreboot/+/68471/comment/ffbf67f0_60dc58e2
PS44, Line 4: // Table | A | B | C | D | E | F | First boot |
trailing whitespace
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PS44, Line 9:
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