coreboot-gerrit November 2022

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[XL] Change in coreboot[master]: payloads/cbflashrom: Add new payload CBFlashrom
by Iman Bingi (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Iman Bingi. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69328 to look at the new patch set (#12). Change subject: payloads/cbflashrom: Add new payload CBFlashrom ...................................................................... payloads/cbflashrom: Add new payload CBFlashrom Flashrom with Graphical User Interface. Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Support for FAT32 file system (USB drives) * Works as ELF payload * Works as Seabios secondary payload * Runs in qemu and on real hardware Shortcomings: * Doesn't work in VGA text mode * Untested TODO: * Test on as many hardware/platforms as possible Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig A payloads/cbflashrom/.gitignore A payloads/cbflashrom/Kconfig A payloads/cbflashrom/Makefile A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.c A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.h A payloads/cbflashrom/NuklearUI/NuklearCheckbox.c A payloads/cbflashrom/NuklearUI/NuklearCheckbox.h A payloads/cbflashrom/NuklearUI/NuklearCommon.h A payloads/cbflashrom/NuklearUI/NuklearDataGrid.c A payloads/cbflashrom/NuklearUI/NuklearDataGrid.h A payloads/cbflashrom/NuklearUI/NuklearFieldFile.c A payloads/cbflashrom/NuklearUI/NuklearFieldFile.h A payloads/cbflashrom/NuklearUI/NuklearFieldHex.c A payloads/cbflashrom/NuklearUI/NuklearFieldHex.h A payloads/cbflashrom/NuklearUI/NuklearFileChooser.c A payloads/cbflashrom/NuklearUI/NuklearFileChooser.h A payloads/cbflashrom/NuklearUI/NuklearHex.c A payloads/cbflashrom/NuklearUI/NuklearHex.h A payloads/cbflashrom/NuklearUI/NuklearInput.c A payloads/cbflashrom/NuklearUI/NuklearInput.h A payloads/cbflashrom/NuklearUI/NuklearObject.c A payloads/cbflashrom/NuklearUI/NuklearObject.h A payloads/cbflashrom/NuklearUI/NuklearStyle.c A payloads/cbflashrom/NuklearUI/NuklearStyle.h A payloads/cbflashrom/NuklearUI/NuklearUI.h A payloads/cbflashrom/arch/x86/cpuid.c A payloads/cbflashrom/arch/x86/cpuid.h A payloads/cbflashrom/arch/x86/memcpy.c A payloads/cbflashrom/arch/x86/memcpy.h A payloads/cbflashrom/cbflashrom.c A payloads/cbflashrom/cbflashrom.h A payloads/cbflashrom/flashrom/82802ab.c A payloads/cbflashrom/flashrom/COPYING A payloads/cbflashrom/flashrom/Doxyfile A payloads/cbflashrom/flashrom/MAINTAINERS A payloads/cbflashrom/flashrom/Makefile A payloads/cbflashrom/flashrom/Makefile.include A payloads/cbflashrom/flashrom/README A payloads/cbflashrom/flashrom/amd_imc.c A payloads/cbflashrom/flashrom/at45db.c A payloads/cbflashrom/flashrom/atahpt.c A payloads/cbflashrom/flashrom/atavia.c A payloads/cbflashrom/flashrom/bitbang_spi.c A payloads/cbflashrom/flashrom/board_enable.c A payloads/cbflashrom/flashrom/buspirate_spi.c A payloads/cbflashrom/flashrom/cbtable.c A payloads/cbflashrom/flashrom/ch341a_spi.c A payloads/cbflashrom/flashrom/chipset_enable.c A payloads/cbflashrom/flashrom/cli_common.c A payloads/cbflashrom/flashrom/cli_output.c A payloads/cbflashrom/flashrom/custom_baud.c A payloads/cbflashrom/flashrom/dediprog.c A payloads/cbflashrom/flashrom/developerbox_spi.c A payloads/cbflashrom/flashrom/digilent_spi.c A payloads/cbflashrom/flashrom/dirtyjtag_spi.c A payloads/cbflashrom/flashrom/dmi.c A payloads/cbflashrom/flashrom/drkaiser.c A payloads/cbflashrom/flashrom/edi.c A payloads/cbflashrom/flashrom/en29lv640b.c A payloads/cbflashrom/flashrom/flashchips.c A payloads/cbflashrom/flashrom/flashrom.8.tmpl A payloads/cbflashrom/flashrom/flashrom.c A payloads/cbflashrom/flashrom/fmap.c A payloads/cbflashrom/flashrom/ft2232_spi.c A payloads/cbflashrom/flashrom/gfxnvidia.c A payloads/cbflashrom/flashrom/helpers.c A payloads/cbflashrom/flashrom/helpers_fileio.c A payloads/cbflashrom/flashrom/hwaccess_physmap.c A payloads/cbflashrom/flashrom/hwaccess_x86_io.c A payloads/cbflashrom/flashrom/hwaccess_x86_msr.c A payloads/cbflashrom/flashrom/ich_descriptors.c A payloads/cbflashrom/flashrom/ichspi.c A payloads/cbflashrom/flashrom/include/chipdrivers.h A payloads/cbflashrom/flashrom/include/coreboot_tables.h A payloads/cbflashrom/flashrom/include/custom_baud.h A payloads/cbflashrom/flashrom/include/edi.h A payloads/cbflashrom/flashrom/include/ene.h A payloads/cbflashrom/flashrom/include/flash.h A payloads/cbflashrom/flashrom/include/flashchips.h A payloads/cbflashrom/flashrom/include/fmap.h A payloads/cbflashrom/flashrom/include/hwaccess_physmap.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_io.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_msr.h A payloads/cbflashrom/flashrom/include/i2c_helper.h A payloads/cbflashrom/flashrom/include/ich_descriptors.h A payloads/cbflashrom/flashrom/include/layout.h A payloads/cbflashrom/flashrom/include/libflashrom.h A payloads/cbflashrom/flashrom/include/platform.h A payloads/cbflashrom/flashrom/include/platform/pci.h A payloads/cbflashrom/flashrom/include/platform/swap.h A payloads/cbflashrom/flashrom/include/programmer.h A payloads/cbflashrom/flashrom/include/spi.h A payloads/cbflashrom/flashrom/include/usb_device.h A payloads/cbflashrom/flashrom/include/writeprotect.h A payloads/cbflashrom/flashrom/internal.c A payloads/cbflashrom/flashrom/internal.h A payloads/cbflashrom/flashrom/it8212.c A payloads/cbflashrom/flashrom/it87spi.c A payloads/cbflashrom/flashrom/jedec.c A payloads/cbflashrom/flashrom/jlink_spi.c A payloads/cbflashrom/flashrom/known_boards.c A payloads/cbflashrom/flashrom/layout.c A payloads/cbflashrom/flashrom/libflashrom.c A payloads/cbflashrom/flashrom/libflashrom.map A payloads/cbflashrom/flashrom/mcp6x_spi.c A payloads/cbflashrom/flashrom/meson.build A payloads/cbflashrom/flashrom/meson_options.txt A payloads/cbflashrom/flashrom/mstarddc_spi.c A payloads/cbflashrom/flashrom/nic3com.c A payloads/cbflashrom/flashrom/nicintel.c A payloads/cbflashrom/flashrom/nicintel_eeprom.c A payloads/cbflashrom/flashrom/nicintel_spi.c A payloads/cbflashrom/flashrom/nicnatsemi.c A payloads/cbflashrom/flashrom/nicrealtek.c A payloads/cbflashrom/flashrom/ogp_spi.c A payloads/cbflashrom/flashrom/opaque.c A payloads/cbflashrom/flashrom/parade_lspcon.c A payloads/cbflashrom/flashrom/parallel.c A payloads/cbflashrom/flashrom/pcidev.c A payloads/cbflashrom/flashrom/pickit2_spi.c A payloads/cbflashrom/flashrom/platform/endian_big.c A payloads/cbflashrom/flashrom/platform/endian_little.c A payloads/cbflashrom/flashrom/platform/memaccess.c A payloads/cbflashrom/flashrom/platform/meson.build A payloads/cbflashrom/flashrom/pony_spi.c A payloads/cbflashrom/flashrom/processor_enable.c A payloads/cbflashrom/flashrom/programmer.c A payloads/cbflashrom/flashrom/programmer_table.c A payloads/cbflashrom/flashrom/raiden_debug_spi.c A payloads/cbflashrom/flashrom/rayer_spi.c A payloads/cbflashrom/flashrom/realtek_mst_i2c_spi.c A payloads/cbflashrom/flashrom/s25f.c A payloads/cbflashrom/flashrom/satamv.c A payloads/cbflashrom/flashrom/satasii.c A payloads/cbflashrom/flashrom/sb600spi.c A payloads/cbflashrom/flashrom/serprog.c A payloads/cbflashrom/flashrom/sfdp.c A payloads/cbflashrom/flashrom/spi.c A payloads/cbflashrom/flashrom/spi25.c A payloads/cbflashrom/flashrom/spi25_statusreg.c A payloads/cbflashrom/flashrom/spi95.c A payloads/cbflashrom/flashrom/sst28sf040.c A payloads/cbflashrom/flashrom/sst49lfxxxc.c A payloads/cbflashrom/flashrom/sst_fwhub.c A payloads/cbflashrom/flashrom/stlinkv3_spi.c A payloads/cbflashrom/flashrom/stm50.c A payloads/cbflashrom/flashrom/test_build.sh A payloads/cbflashrom/flashrom/udelay.c A payloads/cbflashrom/flashrom/usb_device.c A payloads/cbflashrom/flashrom/usbblaster_spi.c A payloads/cbflashrom/flashrom/usbdev.c A payloads/cbflashrom/flashrom/w29ee011.c A payloads/cbflashrom/flashrom/w39.c A payloads/cbflashrom/flashrom/wbsio_spi.c A payloads/cbflashrom/flashrom/writeprotect.c A payloads/cbflashrom/flashrom/writeprotect_ranges.c A payloads/cbflashrom/fsys/usbstorage.c A payloads/cbflashrom/fsys/usbstorage.h A payloads/cbflashrom/gfx/gfx.c A payloads/cbflashrom/gfx/gfx.h A payloads/cbflashrom/gfx/splash.c A payloads/cbflashrom/gfx/splash.h A payloads/cbflashrom/lang/en.c A payloads/cbflashrom/lang/lang.c A payloads/cbflashrom/lang/lang.h A payloads/cbflashrom/libftdi/LICENSE A payloads/cbflashrom/libftdi/src/ftdi.c A payloads/cbflashrom/libftdi/src/ftdi.h A payloads/cbflashrom/libftdi/src/ftdi_i.h A payloads/cbflashrom/libftdi/src/ftdi_stream.c A payloads/cbflashrom/libjaylink/buffer.c A payloads/cbflashrom/libjaylink/core.c A payloads/cbflashrom/libjaylink/device.c A payloads/cbflashrom/libjaylink/discovery.c A payloads/cbflashrom/libjaylink/discovery_usb.c A payloads/cbflashrom/libjaylink/emucom.c A payloads/cbflashrom/libjaylink/error.c A payloads/cbflashrom/libjaylink/fileio.c A payloads/cbflashrom/libjaylink/jtag.c A payloads/cbflashrom/libjaylink/libjaylink-internal.h A payloads/cbflashrom/libjaylink/libjaylink.h A payloads/cbflashrom/libjaylink/list.c A payloads/cbflashrom/libjaylink/log.c A payloads/cbflashrom/libjaylink/strutil.c A payloads/cbflashrom/libjaylink/swd.c A payloads/cbflashrom/libjaylink/swo.c A payloads/cbflashrom/libjaylink/target.c A payloads/cbflashrom/libjaylink/transport.c A payloads/cbflashrom/libjaylink/transport_usb.c A payloads/cbflashrom/libjaylink/util.c A payloads/cbflashrom/libusb/libusb.c A payloads/cbflashrom/libusb/libusb.h A payloads/cbflashrom/logo/cbui.png A payloads/cbflashrom/lp.config A payloads/cbflashrom/util/buffers.c A payloads/cbflashrom/util/buffers.h A payloads/cbflashrom/util/vector.c A payloads/cbflashrom/util/vector.h 199 files changed, 91,908 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/69328/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/69328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Gerrit-Change-Number: 69328 Gerrit-PatchSet: 12 Gerrit-Owner: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by build bot (Jenkins) (Code Review) 21 Nov '22

21 Nov '22

1 0

[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505
by build bot (Jenkins) (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69759 ) Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505 ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164114): https://review.coreboot.org/c/coreboot/+/69759/comment/6b56f6e8_6b812e07 PS3, Line 42: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 04:42:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by Kyösti Mälkki (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Kyösti Mälkki, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu. Hello build bot (Jenkins), Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69760 to look at the new patch set (#4). Change subject: [NOTFORMERGE] squashed intel pmutil ops ...................................................................... [NOTFORMERGE] squashed intel pmutil ops Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/include/arch/io_bitops.h M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/mainboard/asus/p2b/variants/p3b-f/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/samsung/lumpy/smihandler.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/security/intel/txt/romstage.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmclib.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c A src/southbridge/intel/common/tco.c M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lp_gpio.c A src/southbridge/intel/lynxpoint/lp_gpio_ops.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 147 files changed, 1,130 insertions(+), 1,120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69760/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Gerrit-Change-Number: 69760 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505
by Kyösti Mälkki (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69759 to look at the new patch set (#3). Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505 ...................................................................... [NOTFORMERGE] aopen,smm,i82801,e7505 Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 16 files changed, 252 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/69759/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by build bot (Jenkins) (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Angel Pons, Patrick Rudolph, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61517 ) Change subject: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... Patch Set 6: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164113): https://review.coreboot.org/c/coreboot/+/61517/comment/4b01e00b_67de9044 PS6, Line 13: 'occuring' may be misspelled - perhaps 'occurring'? File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164113): https://review.coreboot.org/c/coreboot/+/61517/comment/763718dd_866b70d2 PS6, Line 42: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 21 Nov 2022 04:26:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by Kyösti Mälkki (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Angel Pons, Patrick Rudolph, Elyes Haouas. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61517 to look at the new patch set (#6). Change subject: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occuring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 16 files changed, 257 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61517/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/amd: Define post codes
by Martin L Roth (Code Review) 21 Nov '22

21 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69867 ) Change subject: soc/amd: Define post codes ...................................................................... soc/amd: Define post codes For the most part, this doesn't change any post codes, simply making the existing post-codes into macros. picasso/romstage.c did get a couple of post codes removed to match the other files. The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global at some point, while the POST_AGESA and POST_PSP codes would stay AMD specific. Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S A src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/morgana/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c 11 files changed, 85 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/69867/1 diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 251e23a..b38ce80 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,6 +8,7 @@ ****************************************************************************** */ +#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h> .section .init @@ -27,7 +28,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) AMD_ENABLE_STACK @@ -41,7 +42,7 @@ pushl %eax /* tsc[31:0] */ before_carstage: - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 503de3b..e123c36 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/post_codes.h> #include <cpu/x86/post_code.h> .section .init, "ax", @progbits .global bootblock_resume_entry bootblock_resume_entry: - post_code(0xb0) + post_code(POST_BOOTBLOCK_RESUME_ENTRY) /* Get an early timestamp */ rdtsc @@ -23,7 +24,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0xa0) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) #if ENV_X86_64 #include <cpu/x86/64bit/entry64.inc> @@ -56,7 +57,7 @@ pushl %eax /* tsc[31:0] */ #endif - post_code(0xa2) + post_code(POST_BOOTBLOCK_PRE_C_DONE) call bootblock_c_entry /* Never reached */ diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h new file mode 100644 index 0000000..463f57a --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_POST_CODES_H +#define AMD_BLOCK_POST_CODES_H + +#define POST_AGESA_AMDINITRESET 0x37 +#define POST_AGESA_AMDINITEARLY 0x38 + +#define POST_ROMSTAGE_MAIN 0x40 + +#define POST_AGESA_AMDINITPOST 0x40 +#define POST_AGESA_AMDINITPOST_DONE 0x41 + +#define POST_PSP_NOTIFY_DRAM 0x42 +#define POST_PSP_NOTIFY_DRAM 0x43 + +#define POST_ROMSTAGE_RUN_POSTCAR 0x44 + +#define POST_PSP_LOAD_SMU 0x46 +#define POST_AGESA_AMDINITENV 0x47 +#define POST_AGESA_AMDS3LATERESTORE 0x48 + +#define POST_AGESA_AMDINITRESUME 0x60 +#define POST_AGESA_AMDINITRESUME_DONE 0x61 + +#define POST_BOOTBLOCK_SOC_EARLY_INIT 0x90 + + +#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0 +#define POST_BOOTBLOCK_PRE_C_ENTRY 0xa0 +#define POST_BOOTBLOCK_PRE_C_DONE 0xa2 + +#endif diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/glinda/romstage.c +++ b/src/soc/amd/glinda/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c index 3548a79..0ca32ba 100644 --- a/src/soc/amd/mendocino/romstage.c +++ b/src/soc/amd/mendocino/romstage.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <amdblocks/stb.h> #include <console/console.h> #include <cpu/cpu.h> @@ -15,7 +16,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE)) write_stb_to_console(); diff --git a/src/soc/amd/morgana/romstage.c b/src/soc/amd/morgana/romstage.c index b843bff..2bf5e23 100644 --- a/src/soc/amd/morgana/romstage.c +++ b/src/soc/amd/morgana/romstage.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <console/console.h> #include <cpu/cpu.h> #include <fsp/api.h> @@ -12,7 +13,7 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call */ fill_chipset_state(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 9958af2..846460d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <amdblocks/memmap.h> #include <amdblocks/pmlib.h> +#include <amdblocks/post_codes.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> @@ -13,16 +14,14 @@ void __noreturn romstage_main(void) { - post_code(0x40); + post_code(POST_ROMSTAGE_MAIN); /* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); - post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); memmap_stash_early_dram_usage(); - post_code(0x44); run_ramstage(); } diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 0a67d9b..f5451f85 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -13,6 +13,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <amdblocks/iomap.h> +#include <amdblocks/post_codes.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> @@ -77,7 +78,7 @@ void bootblock_soc_early_init(void) { bootblock_fch_early_init(); - post_code(0x90); + post_code(POST_BOOTBLOCK_SOC_EARLY_INIT); } void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1633ecd..0a530fc 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -15,6 +15,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> #include <amdblocks/i2c.h> +#include <amdblocks/post_codes.h> #include "chip.h" @@ -115,15 +116,15 @@ static void earliest_ramstage(void *unused) { if (!acpi_is_wakeup_s3()) { - post_code(0x46); + post_code(POST_PSP_LOAD_SMU); if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2"); - post_code(0x47); + post_code(POST_AGESA_AMDINITENV); do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); } else { /* Complete the initial system restoration */ - post_code(0x46); + post_code(POST_AGESA_AMDS3LATERESTORE); do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); } } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 54fc51e..efa256f 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -5,6 +5,7 @@ #include <amdblocks/agesawrapper_call.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/biosram.h> +#include <amdblocks/post_codes.h> #include <amdblocks/psp.h> #include <arch/romstage.h> #include <cbmem.h> @@ -35,10 +36,10 @@ static void agesa_call(void) { - post_code(0x37); + post_code(POST_AGESA_AMDINITRESET); do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - post_code(0x38); + post_code(POST_AGESA_AMDINITEARLY); /* APs will not exit amdinitearly */ do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); } @@ -66,10 +67,10 @@ bsp_agesa_call(); if (!s3_resume) { - post_code(0x40); + post_code(POST_AGESA_AMDINITPOST); do_agesawrapper(AMD_INIT_POST, "amdinitpost"); - post_code(0x41); + post_code(POST_AGESA_AMDINITPOST_DONE); /* * TODO: This is a hack to work around current AGESA behavior. * AGESA needs to change to reflect that coreboot owns @@ -99,16 +100,16 @@ wrmsr(SYSCFG_MSR, sys_cfg); } else { printk(BIOS_INFO, "S3 detected\n"); - post_code(0x60); + post_code(POST_AGESA_AMDINITRESUME); do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); - post_code(0x61); + post_code(POST_AGESA_AMDINITRESUME_DONE); } - post_code(0x42); + post_code(POST_PSP_NOTIFY_DRAM); psp_notify_dram(); - post_code(0x43); + post_code(POST_PSP_NOTIFY_DRAM_DONE); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) @@ -117,7 +118,7 @@ if (CONFIG(SMM_TSEG)) smm_list_regions(); - post_code(0x44); + post_code(POST_ROMSTAGE_RUN_POSTCAR); prepare_and_run_postcar(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7 Gerrit-Change-Number: 69867 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/intel/car: Define post codes
by Martin L Roth (Code Review) 21 Nov '22

21 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69866 ) Change subject: cpu/intel/car: Define post codes ...................................................................... cpu/intel/car: Define post codes This moves a lot of post code values, but unifies them between platforms, so that the same value means the same thing as much as possible. The P4-netburst code was the most extensive and most different, so that dictated the majority of the values. Three were two values there that didn't match the other files, so those two values, 0x22 & 0x29 have duplicate entries in the table. The rest of the entries are similar between platforms, though the values for many of them were moved to match the P4-netburst values. POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become global, while POST_SOC would be specific to the Intel platforms. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S A src/cpu/intel/car/post_codes.h 7 files changed, 115 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/69866/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f47ba5f..724fe1c 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include "../../post_codes.h" + .section .init .global bootblock_pre_c_entry @@ -15,7 +17,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -28,7 +30,7 @@ bt $12, %eax jc wait_for_sipi - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -57,7 +59,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x22) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -82,7 +84,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -90,7 +92,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -98,7 +100,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -126,7 +128,7 @@ shr $2, %ecx rep stosl - post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -145,7 +147,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -179,7 +181,7 @@ #endif before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 0451bb4..7d6eea2 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include "../../post_codes.h" + #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e @@ -20,7 +22,7 @@ jmp check_mtrr /* Check if CPU properly reset */ cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -33,14 +35,14 @@ bt $12, %eax jc wait_for_sipi - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -86,7 +88,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl car_mtrr_start, %eax @@ -94,7 +96,7 @@ xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -115,7 +117,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -186,7 +188,7 @@ orl $3, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -197,7 +199,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -232,7 +234,7 @@ #endif before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76..bdcac29 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include "../../post_codes.h" + #define NoEvictMod_MSR 0x2e0 .code32 @@ -12,14 +14,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -35,7 +37,7 @@ andl $~1, %eax wrmsr - post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 887bb22..f14a8f2 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include "../../post_codes.h" + .section .init .global bootblock_pre_c_entry @@ -13,7 +15,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -41,7 +43,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -49,7 +51,7 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -67,7 +69,7 @@ movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -83,7 +85,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -91,7 +93,7 @@ orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -113,7 +115,7 @@ xorl %eax, %eax rep stosl - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -132,7 +134,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -155,7 +157,7 @@ pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9ac9e22..189e702 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -5,6 +5,8 @@ #include <cpu/x86/post_code.h> #include <cpu/x86/lapic_def.h> +#include "../../post_codes.h" + /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) @@ -19,7 +21,7 @@ bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -52,7 +54,7 @@ inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -60,7 +62,7 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. @@ -104,7 +106,7 @@ bsp_init: - post_code(0x23) + post_code(POST_SOC_BSP_INIT) /* Send INIT IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -118,7 +120,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b - post_code(0x24) + post_code(POST_SOC_COUNT_CORES) movl $1, %eax cpuid @@ -153,7 +155,7 @@ hyper_threading_cpu: - post_code(0x25) + post_code(POST_SOC_CPU_HYPER_THREADING) /* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -168,7 +170,7 @@ andl $LAPIC_ICR_BUSY, %ecx jnz 1b - post_code(0x26) + post_code(POST_SOC_CPU_SIBLING_DELAY) /* Wait for sibling CPU to start. */ 1: movl $(MTRR_PHYS_BASE(0)), %ecx @@ -184,14 +186,14 @@ ap_init: - post_code(0x27) + post_code(POST_SOC_CPU_AP_INIT) /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - post_code(0x28) + post_code(POST_SOC_SET_MTRR_BASE) /* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -199,7 +201,7 @@ xorl %edx, %edx wrmsr - post_code(0x29) + post_code(POST_SOC_AP_HALT) ap_halt: cli @@ -210,7 +212,7 @@ sipi_complete: - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -226,7 +228,7 @@ orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -269,7 +271,7 @@ wrmsr no_msr_11e: - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx @@ -296,7 +298,7 @@ jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -336,7 +338,7 @@ wrmsr fill_cache: - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -379,7 +381,7 @@ #endif before_c_entry: - post_code(0x2f) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342f..1fffaa2 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -4,20 +4,22 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include "../../post_codes.h" + .code32 .global chipset_teardown_car chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -25,7 +27,7 @@ andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/post_codes.h b/src/cpu/intel/car/post_codes.h new file mode 100644 index 0000000..3db0aeb --- /dev/null +++ b/src/cpu/intel/car/post_codes.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CPU_INTEL_CAR_POST_CODES_H +#define CPU_INTEL_CAR_POST_CODES_H + +#define POST_BOOTBLOCK_CAR 0x20 +#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POST_SOC_BSP_INIT 0x23 +#define POST_SOC_COUNT_CORES 0x24 +#define POST_SOC_CPU_HYPER_THREADING 0x25 +#define POST_SOC_CPU_SIBLING_DELAY 0x26 +#define POST_SOC_CPU_AP_INIT 0x27 +#define POST_SOC_SET_MTRR_BASE 0x28 +#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POST_SOC_AP_HALT 0x29 +#define POST_SOC_SET_CAR_BASE 0x2a +#define POST_SOC_ENABLE_MTRRS 0x2b +#define POST_SOC_ENABLE_CACHE 0x2c +#define POST_SOC_DISABLE_CACHE 0x2d +#define POST_SOC_FILL_CACHE 0x2e +#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f + +#define POST_POSTCAR_DISABLE_CACHE 0x30 +#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POST_POSTCAR_TEARDOWN_DONE 0x32 + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 Gerrit-Change-Number: 69866 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/intel/common: Define post codes
by Martin L Roth (Code Review) 21 Nov '22

21 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69865 ) Change subject: soc/intel/common: Define post codes ...................................................................... soc/intel/common: Define post codes For the most part, this just moves the existing post codes into macros so that they're not just bare numbers. cache_as_ram.S: Post code 0x28 was previously pointless with just a single jump between it and post code 0x29, car_init_done. This code was removed, and the 0x28 value was used to differentiate the car_nem_enhanced subroutine from the other 0x26 post codes used before calling the clear_car subroutine. All other post codes remain identical. POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas the POST_SOC codes are expected to be Intel only. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/common/block/cse/cse.c A src/soc/intel/common/block/include/intelblocks/post_codes.h 4 files changed, 68 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69865/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 552ba15..1b08af2 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -8,6 +8,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <intelblocks/msr.h> +#include <intelblocks/post_codes.h> .section .init, "ax", @progbits @@ -77,7 +78,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0x20) + post_code(POST_BOOTBLOCK_PRE_C_ENTRY) /* Bootguard sets up its own CAR and needs separate handling */ check_boot_guard: @@ -97,7 +98,7 @@ jmp check_mtrr /* Check if CPU properly reset */ no_reset: - post_code(0x21) + post_code(POST_SOC_NO_RESET) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -110,7 +111,7 @@ wrmsr jnz clear_fixed_mtrr - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -128,7 +129,7 @@ dec %ebx jnz clear_var_mtrr - post_code(0x23) + post_code(POST_SOC_CLEAR_VAR_MTRRS) /* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -156,7 +157,7 @@ bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - post_code(0x24) + post_code(POST_SOC_SET_UP_CAR_MTRRS) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) find_free_mtrr @@ -215,7 +216,7 @@ #else #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" #endif - post_code(0x25) + post_code(POST_SOC_BOOTGUARD_SETUP) is_bootguard_nem jz no_bootguard_car_continue @@ -267,7 +268,7 @@ .global car_init_done car_init_done: - post_code(0x29) + post_code(POST_SOC_CAR_INIT_DONE) /* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -294,7 +295,7 @@ #endif before_carstage: - post_code(0x2a) + post_code(POST_SOC_BEFORE_CARSTAGE) call bootblock_c_entry /* Never reached */ @@ -327,11 +328,11 @@ or $0x1, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_CLEARING_CAR) clear_car - post_code(0x27) + post_code(POST_SOC_DISABLE_CACHE_EVICT) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -339,8 +340,6 @@ or $0x2, %eax wrmsr - post_code(0x28) - jmp car_init_done #elif CONFIG(INTEL_CAR_CQOS) @@ -418,11 +417,11 @@ and %ebx, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_CLEARING_CAR) clear_car - post_code(0x27) + post_code(POST_SOC_DISABLE_CACHE_EVICT) /* Cache is populated. Use mask 1 that will block evicts */ mov $IA32_PQR_ASSOC, %ecx @@ -437,8 +436,6 @@ and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax wrmsr - post_code(0x28) - jmp car_init_done #elif CONFIG(INTEL_CAR_NEM_ENHANCED) @@ -449,7 +446,7 @@ rdmsr or $0x1, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_CAR_NEM_ENHANCED) /* Create n-way set associativity of cache */ xorl %edi, %edi @@ -636,7 +633,7 @@ #endif wrmsr - post_code(0x27) + post_code(POST_SOC_DISABLE_CACHE_EVICT) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. @@ -647,7 +644,5 @@ orl $0x02, %eax wrmsr - post_code(0x28) - jmp car_init_done #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 173ebf7..0126a12 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -3,6 +3,7 @@ #include <device/pci_def.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> +#include <intelblocks/post_codes.h> #define CBFS_FILE_MAGIC 0 #define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) @@ -19,7 +20,7 @@ .global cache_as_ram cache_as_ram: - post_code(0x21) + post_code(POST_BOOTBLOCK_CAR) movl $(CONFIG_FSP_T_LOCATION), %ebx add $0x94, %ebx diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ceb75e2..c2d4484 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/post_codes.h> #include <option.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> @@ -611,7 +612,7 @@ uint32_t csr; /* Clear post code to prevent eventlog entry from unknown code. */ - post_code(0); + post_code(POST_CODE_ZERO); /* Send reset request */ csr = read_host_csr(); diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h new file mode 100644 index 0000000..851e36f --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_POST_CODES_H +#define SOC_INTEL_COMMON_BLOCK_POST_CODES_H + +/* common/block/cpu/car/cache_as_ram.s */ +#define POST_BOOTBLOCK_PRE_C_ENTRY 0x20 +#define POST_SOC_NO_RESET 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 +#define POST_SOC_CLEAR_VAR_MTRRS 0x23 +#define POST_SOC_SET_UP_CAR_MTRRS 0x24 +#define POST_SOC_BOOTGUARD_SETUP 0x25 +#define POST_SOC_CLEARING_CAR 0x26 +#define POST_SOC_DISABLE_CACHE_EVICT 0x27 +#define POST_SOC_CAR_NEM_ENHANCED 0x28 +#define POST_SOC_CAR_INIT_DONE 0x29 +#define POST_SOC_BEFORE_CARSTAGE 0x2A + +/* common/block/cpu/car/cache_as_ram_fsp.S */ +#define POST_BOOTBLOCK_CAR 0x21 + +/* common/block/cse/cse.c */ +#define POST_CODE_ZERO 0x00 +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab Gerrit-Change-Number: 69865 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022