coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: intelblocks/cse: Add functions to check and change PTT state
by Michał Żygowski (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Michał Kopeć. Hello build bot (Jenkins), Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68919 to look at the new patch set (#3). Change subject: intelblocks/cse: Add functions to check and change PTT state ...................................................................... intelblocks/cse: Add functions to check and change PTT state Add functions that allow checking and changing PTT state at runtime. Can be useful for platforms that want to use dTPM instead and have no means to stitch ME firmware binary with disabled PTT. The changing function also checks for the current feature states via HECI to ensure that the feature state will not be changed if not needed. TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68919/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028 Gerrit-Change-Number: 68919 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vboot: Fix hash digest size, padding and comparison
by Yu-Ping Wu (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Jakub Czapiga, Caveh Jalali, Julius Werner, Boris Mittelberg. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69762 ) Change subject: vboot: Fix hash digest size, padding and comparison ...................................................................... Patch Set 3: (2 comments) File src/ec/google/chromeec/vboot_storage.c: https://review.coreboot.org/c/coreboot/+/69762/comment/b1648d64_42dc3fbc PS2, Line 21: memset(data, 0, sizeof(data)); > There is a slot number check and max data size check. […] With ``` struct ec_params_vstore_write req = { .slot = slot, }; ``` I think the unspecified field `.data` will be zero. https://review.coreboot.org/c/coreboot/+/69762/comment/e509ad7b_8980e755 PS2, Line 50: assert(digest_size == EC_VSTORE_SLOT_SIZE); > It has to stay. […] Right. -- To view, visit https://review.coreboot.org/c/coreboot/+/69762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Gerrit-Change-Number: 69762 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 13:25:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/msi/ms7d25: Add support for DDR5 variant
by Michał Żygowski (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Felix Singer, Paul Menzel, Michał Kopeć, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68448 ) Change subject: mb/msi/ms7d25: Add support for DDR5 variant ...................................................................... Patch Set 7: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68448/comment/ccdf2ffc_cf8caf9e PS7, Line 10: difference is the board's DDR5 memory design. > Why not, in the dmidecode outputs, I can see that the original firmware initialized the revision to […] We also have the PCB rev 2.1, but SMBIOS reports 2.0, I have set the default to 2.0, people may always override it via menuconfig Patchset: PS7: > They are the same. It has been checked. Ack File configs/config.dell_precision_t1650: PS7: > Yeah.. `$ history`: […] Removed... File src/mainboard/msi/ms7d25/Kconfig: https://review.coreboot.org/c/coreboot/+/68448/comment/94a48693_b4ca2ff6 PS7, Line 35: default "Default string" > Hmmm Yup, vendor firmware leaves such nits... File src/mainboard/msi/ms7d25/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/68448/comment/82ea72e0_a3b5c753 PS7, Line 15: .UserBd = BOARD_TYPE_DESKTOP_2DPC, > No longer FIXME? Makes sense I thought I removed it long time ago, when DESKTOP_2DPC was not defined... Anyways FIXME shouldn't be here any longer. -- To view, visit https://review.coreboot.org/c/coreboot/+/68448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Gerrit-Change-Number: 68448 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 12:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/msi/ms7d25: Add support for DDR5 variant
by Michał Żygowski (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Felix Singer, Michał Żygowski, Paul Menzel, Michał Kopeć, Angel Pons. Hello build bot (Jenkins), Paul Menzel, Michał Kopeć, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68448 to look at the new patch set (#8). Change subject: mb/msi/ms7d25: Add support for DDR5 variant ...................................................................... mb/msi/ms7d25: Add support for DDR5 variant The DDR5 board is almost identical to the DDR4 one. The only major difference is the board's DDR5 memory design. TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory: Crucial CT8G48C40U5.M4A1 in all 4 slots. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I652a879d1616df4708fe4690797ad98384897f53 --- R configs/config.msi_ms7d25_ddr4 A configs/config.msi_ms7d25_ddr5 M src/mainboard/msi/ms7d25/Kconfig M src/mainboard/msi/ms7d25/Kconfig.name M src/mainboard/msi/ms7d25/mainboard.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c 6 files changed, 75 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/68448/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/68448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I652a879d1616df4708fe4690797ad98384897f53 Gerrit-Change-Number: 68448 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/dc309f9e_29ff489d PS2, Line 10: : The learning being made from Alder Lake platform showed that the CSE : EOP cmd response time is highly nondeterministic and letting the EOP : cmd issued by FSP makes the response time even worse. : : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute : (late sending of EOP) to ensure there is ample time for CSE to come : to a state where the response to the EOP is almost immediate. > > >Can you please elaborate how the EOP cmd receiving arch is different between ADL and MTL? > > > > My comment is based on the issue you indicated in the CL's commit message. It seems the current commit message is not relevant directly. > > I have verified today that sending EOP using FSP is still taking longer time and even sending EOP late is no different. My conclusion is, the issue we have seen on ADL is still very much applicable on MTL. I'm marking this comment resolved now and please move the discussion into mailing list or bug, whatever you prefer. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 12:38:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/5f2d9fce_f96224de PS2, Line 10: : The learning being made from Alder Lake platform showed that the CSE : EOP cmd response time is highly nondeterministic and letting the EOP : cmd issued by FSP makes the response time even worse. : : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute : (late sending of EOP) to ensure there is ample time for CSE to come : to a state where the response to the EOP is almost immediate. > >Can you please elaborate how the EOP cmd receiving arch is different between ADL and MTL? > > My comment is based on the issue you indicated in the CL's commit message. It seems the current commit message is not relevant directly. I have verified today that sending EOP using FSP is still taking longer time and even sending EOP late is no different. My conclusion is, the issue we have seen on ADL is still very much applicable on MTL. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 12:36:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/crossgcc: Limit LLVM targets to the needed ones
by Arthur Heymans (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Felix Singer, Arthur Heymans, Martin L Roth, Patrick Georgi. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69841 ) Change subject: util/crossgcc: Limit LLVM targets to the needed ones ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Seems not really necessary to me since the Clang toolchain includes all architectures. Also, the Clang toolchain uses more than 3GB disk space. That's a lot compared to what a GCC toolchain needs. The clang toolchain we build is much more featureful than the bare metal only gcc we build. Limiting target arch is a nice start. Do you have some metrics? -- To view, visit https://review.coreboot.org/c/coreboot/+/69841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9938bf176b5fe2b0a631c3b1ae858f988898a196 Gerrit-Change-Number: 69841 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Nov 2022 12:18:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by EricKY Cheng (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held. EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... Patch Set 31: (1 comment) File src/soc/amd/mendocino/root_complex.c: https://review.coreboot.org/c/coreboot/+/68649/comment/810032b0_bdb6450f PS16, Line 393: #else > Hi all, […] Hi AMD, We have added below values into overridetree.cb. vrm_current_limit_throttle_mA, vrm_maximum_current_limit_throttle_mA, vrm_soc_current_limit_throttle_mA, Could you help to check any other missing values that we need to fill in winterhold's overridetree.cb. -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 31 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 21 Nov 2022 12:03:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by Michał Żygowski (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Michał Żygowski, Michał Kopeć. Hello build bot (Jenkins), Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68944 to look at the new patch set (#5). Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... soc/intel/common/block/oc_wdt: Add OC watchdog common block Add new block for handling overcloking watchdog. The watchdog is present since Skylake or maybe even earlier so it is safe to use with most of the micrarchitectures utilizing intelblocks. Some FSPs are also utilizing OC watchdog so care must be taken when initializing it. Example integration provided in subsequent patch. The goal is to provide coreboot with additional reliability settings. The patch adds the common block for initializing and feeding the watchdog. Timeout is configurable via Kconfig and cannot be set to less than 60 seconds to avoid reset loops when full memory training is needed. The patch also adds support for feeding watchdog in driveless mode, i.e. it utilizies periodic SMI to reload the timeout value and restart the watchdog timer. This is optional and selectable by Kconfig option as well. If the option is not enabled, payload and/or software must ensure to keep feeding the watchdog, otherwise the platform will reset. Common SMM drivers have also been extended with new APM command to reset/reboot platform and additionally allow known reset for reboot and shutdown in SMI handlers. Platforms should use the new APM command in FADT as reboot value via SMI if watchdog is enabled. This however assumes that no software writes directly to 0xcf9 port to reset platform, otherwise the reset will be treated as unexpected one. Example is added in subsequent patch for Alder Lake. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc --- M src/arch/x86/Makefile.inc M src/include/cpu/x86/smm.h A src/soc/intel/common/block/include/intelblocks/oc_wdt.h A src/soc/intel/common/block/oc_wdt/Kconfig A src/soc/intel/common/block/oc_wdt/Makefile.inc A src/soc/intel/common/block/oc_wdt/oc_wdt.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smm.c 8 files changed, 368 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/68944/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
by zanxi chen (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Rui Zhou. zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69848 ) Change subject: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/69848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2 Gerrit-Change-Number: 69848 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 12:01:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022