coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi
by build bot (Jenkins) (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69759 ) Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi ...................................................................... Patch Set 4: (1 comment) File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164196): https://review.coreboot.org/c/coreboot/+/69759/comment/3a0fde1c_bdc09d76 PS4, Line 42: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 21 Nov 2022 17:42:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: [NOTFORMERGE] squashed intel pmutil ops
by Kyösti Mälkki (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Kyösti Mälkki, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu. Hello build bot (Jenkins), Jeff Daly, Jonathan Zhang, Angel Pons, Arthur Heymans, Tarun Tuli, Sean Rhodes, Subrata Banik, Johnny Lin, Kapil Porwal, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69760 to look at the new patch set (#5). Change subject: [NOTFORMERGE] squashed intel pmutil ops ...................................................................... [NOTFORMERGE] squashed intel pmutil ops Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/include/arch/io_bitops.h M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/mainboard/asus/p2b/variants/p3b-f/romstage.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/samsung/lumpy/smihandler.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/security/intel/txt/romstage.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/elog.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pch/Kconfig M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/common/pch/include/intelpch/smbus.h M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/include/soc/soc_util.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/elog.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/elog.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/finalize.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmclib.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c A src/southbridge/intel/common/tco.c M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82371eb/wakeup.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/early_usb.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lp_gpio.c A src/southbridge/intel/lynxpoint/lp_gpio_ops.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 159 files changed, 1,152 insertions(+), 1,137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69760/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b4db32888a6a979eee0cbcdbace97bc188ae71b Gerrit-Change-Number: 69760 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi
by Kyösti Mälkki (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69759 to look at the new patch set (#4). Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi ...................................................................... [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/include/acpi/acpi.h M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/asus/p2b/Kconfig D src/mainboard/asus/p2b/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/morgana/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/quark/Kconfig M src/soc/intel/quark/acpi.c M src/southbridge/intel/common/madt.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/madt.c 38 files changed, 297 insertions(+), 191 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/69759/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Increase CBFS_MCACHE size
by Karthik Ramasubramanian (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Paul Menzel, Jon Murphy, Fred Reitberger. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69827 ) Change subject: soc/amd/mendocino: Increase CBFS_MCACHE size ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69827/comment/f0f8799e_6777598c PS1, Line 12: to required : 14 KiB. > How was the required size determined? Iterative increment of CBFS_MCACHE size until the overflow stopped. Please refer to the snippet of logs in the TEST message. Patchset: PS1: > Hi Karthik, […] Responded in the bug regarding why you observed the failure. PS1: > I assume that the 4KiB is still large enough to hold everything. Yes, currently it is holding fine. We may have to keep an eye on it in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/69827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe Gerrit-Change-Number: 69827 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 17:41:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/i945: Remove apic 0 from devicetree
by Elyes Haouas (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Arthur Heymans, Alexander Couzens, Evgeny Zinoviev. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69299 ) Change subject: nb/intel/i945: Remove apic 0 from devicetree ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: > sin't gigabyte/ga-945gcm-s2l/devicetree. […] Found here https://review.coreboot.org/c/coreboot/+/69303 -- To view, visit https://review.coreboot.org/c/coreboot/+/69299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Gerrit-Change-Number: 69299 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Mon, 21 Nov 2022 17:32:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/i945: Remove apic 0 from devicetree
by Elyes Haouas (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Arthur Heymans, Alexander Couzens, Evgeny Zinoviev. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69299 ) Change subject: nb/intel/i945: Remove apic 0 from devicetree ...................................................................... Patch Set 14: (1 comment) Patchset: PS14: sin't gigabyte/ga-945gcm-s2l/devicetree.cb missing here ? -- To view, visit https://review.coreboot.org/c/coreboot/+/69299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Gerrit-Change-Number: 69299 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Mon, 21 Nov 2022 17:28:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Pass Ti50 IRQ to PSP
by build bot (Jenkins) (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69874 ) Change subject: mb/google/skyrim: Pass Ti50 IRQ to PSP ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164195): https://review.coreboot.org/c/coreboot/+/69874/comment/9e370f5f_519fd445 PS1, Line 17: Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c Gerrit-Change-Number: 69874 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 21 Nov 2022 16:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Pass Ti50 IRQ to PSP
by Mark Hasemeyer (Code Review) 21 Nov '22

21 Nov '22

Mark Hasemeyer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69874 ) Change subject: mb/google/skyrim: Pass Ti50 IRQ to PSP ...................................................................... mb/google/skyrim: Pass Ti50 IRQ to PSP It shouldn't be assumed that all variants of skyrim will use the same gpio for TPM interrupts. Use the PSP's new mailbox command to tell it what gpio the tpm interrupt comes in on. BUG=b:248193764 TEST=tast run <ip> hwsec.TPMContest Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK Use incorrect GPIO in mailbox cmd and verify TPMContest test failed. Signed-off-by: Mark Hasemeyer <markhas(a)google.com> Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c --- M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/69874/1 diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 7708488..d36dfaf 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -2,9 +2,11 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/psp.h> #include <baseboard/variants.h> #include <console/console.h> #include <device/device.h> +#include <drivers/i2c/tpm/chip.h> #include <soc/acpi.h> #include <variant/ec.h> @@ -69,10 +71,19 @@ override_gpios, override_num_gpios); } +static void configure_psp_tpm_gpio(void) +{ + const struct device *ti50_dev = DEV_PTR(ti50); + struct drivers_i2c_tpm_config *cfg = config_of(ti50_dev); + + psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]); +} + static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); mainboard_ec_init(); + configure_psp_tpm_gpio(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 81c76b7..8502c36 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -182,7 +182,7 @@ register "hid" = ""GOOG0005"" register "desc" = ""Ti50 TPM"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_18)" - device i2c 50 on end + device i2c 50 alias ti50 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c Gerrit-Change-Number: 69874 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: mb/*: Replace SNB PCI devices with references from chipset.cb
by build bot (Jenkins) (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69502 ) Change subject: mb/*: Replace SNB PCI devices with references from chipset.cb ...................................................................... Patch Set 3: Verified+1 (8 comments) File src/mainboard/apple/macbookair4_2/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/df2f5bc4_64c33e38 PS3, Line 43: device ref hda on # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/asrock/b75pro3-m/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/1ab3827b_776d50a6 PS3, Line 60: device ref hda on # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/eaa23f6c_912400b7 PS3, Line 33: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/hp/z220_series/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/4ee74040_7e35c3e3 PS3, Line 37: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/l520/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/5a7527db_7fcb3310 PS3, Line 44: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/s230u/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/9dc98650_3941d65c PS3, Line 48: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/t430/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/54cd911e_d4f47af2 PS3, Line 46: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/x131e/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164193): https://review.coreboot.org/c/coreboot/+/69502/comment/094e14e6_c0271440 PS3, Line 58: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' -- To view, visit https://review.coreboot.org/c/coreboot/+/69502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Gerrit-Change-Number: 69502 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Mon, 21 Nov 2022 16:41:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/model_206ax: Remove fake lapic device
by Arthur Heymans (Code Review) 21 Nov '22

21 Nov '22

Attention is currently required from: Tristan Corrick, Angel Pons, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#16) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59316 ) Change subject: cpu/intel/model_206ax: Remove fake lapic device ...................................................................... cpu/intel/model_206ax: Remove fake lapic device Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic deive is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 10 files changed, 49 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59316/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/59316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Gerrit-Change-Number: 59316 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022