coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: cpu/intel/car: Define post codes
by Martin L Roth (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Martin L Roth, Subrata Banik. Hello Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69866 to look at the new patch set (#2). Change subject: cpu/intel/car: Define post codes ...................................................................... cpu/intel/car: Define post codes This moves a lot of post code values, but unifies them between platforms, so that the same value means the same thing as much as possible. The P4-netburst code was the most extensive and most different, so that dictated the majority of the values. Three were two values there that didn't match the other files, so those two values, 0x22 & 0x29 have duplicate entries in the table. The rest of the entries are similar between platforms, though the values for many of them were moved to match the P4-netburst values. POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become global, while POST_SOC would be specific to the Intel platforms. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S A src/include/cpu/intel/post_codes.h 7 files changed, 109 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/69866/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9 Gerrit-Change-Number: 69866 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vboot: Fix hash digest size, padding and comparison
by Yu-Ping Wu (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jakub Czapiga, Caveh Jalali, Julius Werner, Boris Mittelberg. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69762 ) Change subject: vboot: Fix hash digest size, padding and comparison ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/vboot_storage.c: https://review.coreboot.org/c/coreboot/+/69762/comment/91864e84_e59fefdf PS4, Line 21: data, sizeof(data) `digest, digest_size`. `data` is not needed now. -- To view, visit https://review.coreboot.org/c/coreboot/+/69762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Gerrit-Change-Number: 69762 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 01:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in libhwbase[master]: hw-debug: Ensure global variable default are zeros and in .bss
by Jérémy Compostella (Code Review) 22 Nov '22

22 Nov '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/libhwbase/+/69854 ) Change subject: hw-debug: Ensure global variable default are zeros and in .bss ...................................................................... hw-debug: Ensure global variable default are zeros and in .bss Having global variables prevents the inclusion of the library in coreboot romstage. Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Ib23699f3f3446219c34c60ccd9987346e17769f2 --- M debug/hw-debug.adb 1 file changed, 20 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/54/69854/1 diff --git a/debug/hw-debug.adb b/debug/hw-debug.adb index e28eb17..d116860 100644 --- a/debug/hw-debug.adb +++ b/debug/hw-debug.adb @@ -23,8 +23,10 @@ SPARK_Mode => Off is - Start_Of_Line : Boolean := True; - Register_Write_Delay_Nanoseconds : Word64 := 0; + Not_Start_Of_Line : Boolean; + pragma Linker_Section (Not_Start_Of_Line, ".bss"); + Register_Write_Delay_Nanoseconds : Word64; + pragma Linker_Section (Register_Write_Delay_Nanoseconds, ".bss"); type Base_Range is new Positive range 2 .. 16; type Width_Range is new Natural range 0 .. 64; @@ -43,8 +45,8 @@ is Now_US : Int64; begin - if Start_Of_Line then - Start_Of_Line := False; + if not Not_Start_Of_Line then + Not_Start_Of_Line := True; Now_US := Time.Now_US; Debug_Sink.Put_Char ('['); Do_Put_Int64 ((Now_US / 1_000_000) mod 1_000_000); @@ -71,7 +73,7 @@ procedure New_Line is begin HW.Debug_Sink.New_Line; - Start_Of_Line := True; + Not_Start_Of_Line := False; end New_Line; ---------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/libhwbase/+/69854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: Ib23699f3f3446219c34c60ccd9987346e17769f2 Gerrit-Change-Number: 69854 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache
by Reka Norman (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Kangheui Won. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 ) Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68641/comment/d11b7f26_f791bcd6 PS2, Line 40: treeya > I think because of PSP verstage they don't use postcar at all - see `depends on !RESET_VECTOR_IN_RAM […] Done Patchset: PS3: Any thoughts on this? I'd like to get it submitted for nissa at least. I'm happy to make the change for nissa only if you prefer. -- To view, visit https://review.coreboot.org/c/coreboot/+/68641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Gerrit-Change-Number: 68641 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Nov 2022 00:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache
by Reka Norman (Code Review) 22 Nov '22

22 Nov '22

Reka Norman has restored this change. ( https://review.coreboot.org/c/coreboot/+/68641 ) Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/68641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Gerrit-Change-Number: 68641 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: restore

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[M] Change in coreboot[master]: mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino
by Eric Lai (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Tarun Tuli, David Wu, Ren Kuo, Tyler Wang, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69693 ) Change subject: mb/google/brya/var/craask: Modify GPIOs for craaskneto/craaskino ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: @Ren, please pick the https://review.coreboot.org/c/coreboot/+/69790 and remove the SAR_INT. -- To view, visit https://review.coreboot.org/c/coreboot/+/69693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 Gerrit-Change-Number: 69693 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 00:26:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add Vrm setting for SMT
by Tim Van Patten (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Isaac Lee, Paul Menzel, Martin Roth, Eric Peers, Karthikeyan Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69830 ) Change subject: mb/google/skyrim/var/winterhold: Add Vrm setting for SMT ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680 Gerrit-Change-Number: 69830 Gerrit-PatchSet: 9 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Nov 2022 00:24:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by Tim Van Patten (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Martin Roth, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... Patch Set 31: (1 comment) File src/soc/amd/mendocino/root_complex.c: https://review.coreboot.org/c/coreboot/+/68649/comment/42844cdf_20908111 PS16, Line 393: #else > Hi AMD, […] My concern is that the new fields added to `DPTC_INPUTS()` need to be added to `google/skyrim/variants/skyrim/overridetree.cb`, so we write good values. It looks like `slow_ppt_time_constant_s` already exists, so you just need to add _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttSkinTempLimitApu. -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 31 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 22 Nov 2022 00:23:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/intel/mtlrvp: Configure devicetree and GPIOs for Meteor Lake-P
by Eric Lai (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Harsha B R, Haribalaraman Ramasubramanian, Rizwan Qureshi, Sridhar Siricilla, Balaji Manigandan, Krishna P Bhat D, Usha P. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69396 ) Change subject: mb/intel/mtlrvp: Configure devicetree and GPIOs for Meteor Lake-P ...................................................................... Patch Set 10: Code-Review+1 (2 comments) File src/mainboard/intel/mtlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/69396/comment/a7b4d40f_2211c6b0 PS10, Line 67: # RP configuration put RP setting under RP port would be easier to reading. File src/mainboard/intel/mtlrvp/gpio.c: https://review.coreboot.org/c/coreboot/+/69396/comment/3aaac664_fb25ebf1 PS10, Line 3: #include <console/console.h> nit: alphabet order. -- To view, visit https://review.coreboot.org/c/coreboot/+/69396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3173c3f32b36d24467431df3652badd70efeab93 Gerrit-Change-Number: 69396 Gerrit-PatchSet: 10 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 00:23:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Pass Ti50 IRQ to PSP
by Eric Lai (Code Review) 22 Nov '22

22 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Mark Hasemeyer. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69874 ) Change subject: mb/google/skyrim: Pass Ti50 IRQ to PSP ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c Gerrit-Change-Number: 69874 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 22 Nov 2022 00:14:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022