coreboot-gerrit October 2022

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[L] Change in coreboot[master]: [WIP] mb/asrock/z97_extreme6: Add new mainboard
by Angel Pons (Code Review) 06 Oct '22

06 Oct '22

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68188 ) Change subject: [WIP] mb/asrock/z97_extreme6: Add new mainboard ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68188/comment/0c233dc2_7d93ce81 PS1, Line 9: Not even boot-tested. Haswell MRC.bin seems to panic because of the Z97 PCH, but it should be possible to use Broadwell MRC.bin for the time being. Haswell NRI can reach the payload, maybe some IDs are wrong for the PCH HSIO stuff because SATA doesn't work. Other than that, success! -- To view, visit https://review.coreboot.org/c/coreboot/+/68188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Oct 2022 22:58:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Change TPM I2C freqeuncy to 1 MHz
by Reka Norman (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Ian Feng, Kangheui Won, Shou-Chieh Hsu. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68071 ) Change subject: mb/google/nissa/var/xivu: Change TPM I2C freqeuncy to 1 MHz ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: You need to add configs for all the buses, not just I2C0. Otherwise the other buses will default to rise/fall time 0, which will give the wrong frequency. Could you please add configs for the other buses, take measurements on all of them and attach the results to the bug? -- To view, visit https://review.coreboot.org/c/coreboot/+/68071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f712c14978b95f3a4da82d6f1f5fbae1283b17 Gerrit-Change-Number: 68071 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 06 Oct 2022 22:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] mb/asrock/z97_extreme6: Add new mainboard
by Angel Pons (Code Review) 06 Oct '22

06 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68188 ) Change subject: [WIP] mb/asrock/z97_extreme6: Add new mainboard ...................................................................... [WIP] mb/asrock/z97_extreme6: Add new mainboard Not even boot-tested. Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/z97_extreme6/Kconfig A src/mainboard/asrock/z97_extreme6/Kconfig.name A src/mainboard/asrock/z97_extreme6/Makefile.inc A src/mainboard/asrock/z97_extreme6/acpi/ec.asl A src/mainboard/asrock/z97_extreme6/acpi/platform.asl A src/mainboard/asrock/z97_extreme6/acpi/superio.asl A src/mainboard/asrock/z97_extreme6/board_info.txt A src/mainboard/asrock/z97_extreme6/bootblock.c A src/mainboard/asrock/z97_extreme6/data.vbt A src/mainboard/asrock/z97_extreme6/devicetree.cb A src/mainboard/asrock/z97_extreme6/dsdt.asl A src/mainboard/asrock/z97_extreme6/gma-mainboard.ads A src/mainboard/asrock/z97_extreme6/gpio.c A src/mainboard/asrock/z97_extreme6/hda_verb.c A src/mainboard/asrock/z97_extreme6/romstage.c 15 files changed, 525 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/68188/1 diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig new file mode 100644 index 0000000..d969822 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig @@ -0,0 +1,26 @@ +if BOARD_ASROCK_Z97_EXTREME6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + +config CBFS_SIZE + default 0x200000 + +config MAINBOARD_DIR + default "asrock/z97_extreme6" + +config MAINBOARD_PART_NUMBER + default "Z97 Extreme6" + +endif diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig.name b/src/mainboard/asrock/z97_extreme6/Kconfig.name new file mode 100644 index 0000000..1a75148 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_Z97_EXTREME6 + bool "Z97 Extreme6" diff --git a/src/mainboard/asrock/z97_extreme6/Makefile.inc b/src/mainboard/asrock/z97_extreme6/Makefile.inc new file mode 100644 index 0000000..ec8ca22 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z97_extreme6/acpi/ec.asl b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z97_extreme6/acpi/platform.asl b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl new file mode 100644 index 0000000..7da03bf --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/z97_extreme6/acpi/superio.asl b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z97_extreme6/board_info.txt b/src/mainboard/asrock/z97_extreme6/board_info.txt new file mode 100644 index 0000000..bd01474 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z97%20extreme6/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c new file mode 100644 index 0000000..6d397ff --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/bootblock.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) + +/* FIXME: fill this in */ +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x24, 0xfc); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x02); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + //pnp_set_logical_device(ACPI_DEV); + //pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z97_extreme6/data.vbt b/src/mainboard/asrock/z97_extreme6/data.vbt new file mode 100644 index 0000000..6a73a26 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb new file mode 100644 index 0000000..5d9e7ff --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -0,0 +1,117 @@ +chip northbridge/intel/haswell + + # This mainboard has DVI-I + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0 on + chip cpu/intel/haswell + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe graphics + device pci 01.1 on end # FIXME: figure out the PCIe mux spam + device pci 01.2 on end # FIXME: figure out the PCIe mux spam + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" # Super I/O HWM + register "sata_port_map" = "0x3f" + register "gpe0_en_1" = "0x40002246" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 on end # Intel GbE through I218-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: Maybe M.2? + device pci 1c.1 on end # RP #2 + device pci 1c.2 on end # RP #3: Realtek RTL8111 GbE NIC + device pci 1c.3 on end # RP #4: ASM1184e 4-Port PCIe Switch + device pci 1c.4 on end # RP #5 + device pci 1c.5 on end # RP #6 + device pci 1c.6 on end # RP #7: ASM1042A USB 3.0 + device pci 1c.7 on end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x6f + irq 0xe1 = 0x1f + end + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x72 + irq 0xea = 0x00 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x0f + irq 0xf1 = 0x08 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0x9d + end + device pnp 2e.a on # ACPI + # Power RAM in S3 and let the PCH + # handle power failure actions + #irq 0xe4 = 0x70 + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z97_extreme6/dsdt.asl b/src/mainboard/asrock/z97_extreme6/dsdt.asl new file mode 100644 index 0000000..17c44b6 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads new file mode 100644 index 0000000..8c011b7 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this, there's DP, HDMI and DVI-I + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z97_extreme6/gpio.c b/src/mainboard/asrock/z97_extreme6/gpio.c new file mode 100644 index 0000000..1dee18c --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c new file mode 100644 index 0000000..dd31338 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862808, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x80860101), + AZALIA_PIN_CFG(0, 0x05, 0x18560010), + AZALIA_PIN_CFG(0, 0x06, 0x18560010), + AZALIA_PIN_CFG(0, 0x07, 0x18560010), + + /* TODO: Where did the codec on the PCH's HD Audio controller go? */ +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c new file mode 100644 index 0000000..6524077 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/68188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs
by Angel Pons (Code Review) 06 Oct '22

06 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68187 ) Change subject: sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs ...................................................................... sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs The desktop 9 series PCHs should be the same as the 8 series PCHs. Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ids.h M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 8 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68187/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3da7410..95c0fbc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2833,6 +2833,11 @@ #define PCI_DID_INTEL_LPT_C224 0x8c54 #define PCI_DID_INTEL_LPT_C226 0x8c56 #define PCI_DID_INTEL_LPT_H81 0x8c5c +#define PCI_DID_INTEL_LPT_MOBILE_SAMPLE_9 0x8cc1 +#define PCI_DID_INTEL_LPT_DESKTOP_SAMPLE_9 0x8cc2 +#define PCI_DID_INTEL_LPT_HM97 0x8cc3 +#define PCI_DID_INTEL_LPT_Z97 0x8cc4 +#define PCI_DID_INTEL_LPT_H97 0x8cc6 #define PCI_DID_INTEL_LPT_LP_SAMPLE 0x9c41 #define PCI_DID_INTEL_LPT_LP_PREMIUM 0x9c43 #define PCI_DID_INTEL_LPT_LP_MAINSTREAM 0x9c45 @@ -3480,6 +3485,18 @@ #define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07 #define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09 #define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f +#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_9 0x8c80 +#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI_9 0x8c82 +#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1_9 0x8c84 +#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM_9 0x8c86 +#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45_9 0x8c88 +#define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2_9 0x8c0e +#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_9 0x8c81 +#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI_9 0x8c83 +#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1_9 0x8c85 +#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM_9 0x8c87 +#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45_9 0x8c89 +#define PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2_9 0x8c8f #define PCI_DID_INTEL_LPT_LP_SATA_AHCI 0x9c03 #define PCI_DID_INTEL_LPT_LP_SATA_RAID_1 0x9c05 #define PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07 @@ -4135,6 +4152,7 @@ /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 +#define PCI_DID_INTEL_LPT_H_SMBUS_9 0x8ca2 #define PCI_DID_INTEL_LPT_LP_SMBUS 0x9c22 #define PCI_DID_INTEL_WPT_LP_SMBUS 0x9ca2 #define PCI_DID_INTEL_APL_SMBUS 0x5ad4 @@ -4161,10 +4179,13 @@ /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 #define PCI_DID_INTEL_LPT_H_EHCI_2 0x8c2d +#define PCI_DID_INTEL_LPT_H_EHCI_1_9 0x8ca6 +#define PCI_DID_INTEL_LPT_H_EHCI_2_9 0x8cad #define PCI_DID_INTEL_LPT_LP_EHCI 0x9c26 /* Intel XHCI device Ids */ #define PCI_DID_INTEL_LPT_H_XHCI 0x8c31 +#define PCI_DID_INTEL_LPT_H_XHCI_9 0x8cb1 #define PCI_DID_INTEL_LPT_LP_XHCI 0x9c31 #define PCI_DID_INTEL_APL_XHCI 0x5aa8 #define PCI_DID_INTEL_GLK_XHCI 0x31a8 @@ -4236,6 +4257,7 @@ /* Intel AUDIO device Ids */ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 +#define PCI_DID_INTEL_LPT_H_AUDIO_9 0x8ca0 #define PCI_DID_INTEL_LPT_LP_AUDIO 0x9c20 #define PCI_DID_INTEL_APL_AUDIO 0x5a98 #define PCI_DID_INTEL_GLK_AUDIO 0x3198 @@ -4284,6 +4306,7 @@ /* Intel HECI/ME device Ids */ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a +#define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba #define PCI_DID_INTEL_LPT_LP_MEI 0x9c3a #define PCI_DID_INTEL_APL_CSE0 0x5a9a #define PCI_DID_INTEL_GLK_CSE0 0x319a diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index f41b3c2..34f0753 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -122,6 +122,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_AUDIO, + PCI_DID_INTEL_LPT_H_AUDIO_9, PCI_DID_INTEL_LPT_LP_AUDIO, 0 }; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 20e40cb..fdbee34 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -835,6 +835,11 @@ PCI_DID_INTEL_LPT_LP_PREMIUM, PCI_DID_INTEL_LPT_LP_MAINSTREAM, PCI_DID_INTEL_LPT_LP_VALUE, + PCI_DID_INTEL_LPT_MOBILE_SAMPLE_9, + PCI_DID_INTEL_LPT_DESKTOP_SAMPLE_9, + PCI_DID_INTEL_LPT_HM97, + PCI_DID_INTEL_LPT_Z97, + PCI_DID_INTEL_LPT_H97, 0 }; diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 40626c2..f1c83df 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -921,6 +921,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_MEI, + PCI_DID_INTEL_LPT_H_MEI_9, PCI_DID_INTEL_LPT_LP_MEI, 0 }; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 49108ee..b6cbb13 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -231,6 +231,18 @@ PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM, PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45, PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2, + PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_9, + PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI_9, + PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1_9, + PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM_9, + PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45_9, + PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2_9, + PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_9, + PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI_9, + PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1_9, + PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM_9, + PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45_9, + PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2_9, PCI_DID_INTEL_LPT_LP_SATA_AHCI, PCI_DID_INTEL_LPT_LP_SATA_RAID_1, PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM, diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 519afe5..757254e 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -35,6 +35,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_SMBUS, + PCI_DID_INTEL_LPT_H_SMBUS_9, PCI_DID_INTEL_LPT_LP_SMBUS, PCI_DID_INTEL_WPT_LP_SMBUS, 0 diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 8853a14..662a421 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -173,6 +173,8 @@ PCI_DID_INTEL_LPT_LP_EHCI, PCI_DID_INTEL_LPT_H_EHCI_1, PCI_DID_INTEL_LPT_H_EHCI_2, + PCI_DID_INTEL_LPT_H_EHCI_1_9, + PCI_DID_INTEL_LPT_H_EHCI_2_9, 0 }; diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 1219bcc..2660be1 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -343,6 +343,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_LPT_H_XHCI, + PCI_DID_INTEL_LPT_H_XHCI_9, PCI_DID_INTEL_LPT_LP_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/68187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235 Gerrit-Change-Number: 68187 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: util/inteltool: Add support for (non-ULT) Broadwell
by Angel Pons (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Stefan Reinauer. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68186 ) Change subject: util/inteltool: Add support for (non-ULT) Broadwell ...................................................................... util/inteltool: Add support for (non-ULT) Broadwell Add support for traditional (non-ULT) Broadwell. Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/68186/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6b9ff13..cc4454a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -107,6 +107,10 @@ "4th generation (Haswell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D, + "5th generation (Broadwell family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M, + "5th generation (Broadwell family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M, "6th generation (Skylake-H family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 0689438..1968ee9 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -329,6 +329,8 @@ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 36d1197..a536d39 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -206,6 +206,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index d392c28..fb29d32 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -250,6 +250,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: @@ -369,6 +371,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ @@ -496,6 +500,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: -- To view, visit https://review.coreboot.org/c/coreboot/+/68186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Gerrit-Change-Number: 68186 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: util/inteltool: Add 9 series PCH support
by Angel Pons (Code Review) 06 Oct '22

06 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68185 ) Change subject: util/inteltool: Add 9 series PCH support ...................................................................... util/inteltool: Add 9 series PCH support Add the PCI device IDs for 9 series PCHs. Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/iobp.c M util/inteltool/powermgt.c M util/inteltool/rootcmplx.c M util/inteltool/spi.c 7 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/68185/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index dc2ed77..41e8ca4 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -856,6 +856,11 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_C9_MOBILE: + case PCI_DEVICE_ID_INTEL_C9_DESKTOP: + case PCI_DEVICE_ID_INTEL_HM97: + case PCI_DEVICE_ID_INTEL_Z97: + case PCI_DEVICE_ID_INTEL_H97: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = pch_gpio_registers; size = ARRAY_SIZE(pch_gpio_registers); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 25149a5..6b9ff13 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -363,6 +363,11 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C9_MOBILE, "C9 Mobile"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C9_DESKTOP, "C9 Desktop"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM97, "HM97"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z97, "Z97"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H97, "H97"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 8759c6c..0689438 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -277,6 +277,12 @@ #define PCI_DEVICE_ID_INTEL_C226 0x8c56 #define PCI_DEVICE_ID_INTEL_H81 0x8c5c +#define PCI_DEVICE_ID_INTEL_C9_MOBILE 0x8cc1 +#define PCI_DEVICE_ID_INTEL_C9_DESKTOP 0x8cc2 +#define PCI_DEVICE_ID_INTEL_HM97 0x8cc3 +#define PCI_DEVICE_ID_INTEL_Z97 0x8cc4 +#define PCI_DEVICE_ID_INTEL_H97 0x8cc6 + #define PCI_DEVICE_ID_INTEL_82X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 diff --git a/util/inteltool/iobp.c b/util/inteltool/iobp.c index e6c4185..461dbd6 100644 --- a/util/inteltool/iobp.c +++ b/util/inteltool/iobp.c @@ -291,6 +291,11 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_C9_MOBILE: + case PCI_DEVICE_ID_INTEL_C9_DESKTOP: + case PCI_DEVICE_ID_INTEL_HM97: + case PCI_DEVICE_ID_INTEL_Z97: + case PCI_DEVICE_ID_INTEL_H97: iobp_registers = lynxpoint_iobp_registers; iobp_size = ARRAY_SIZE(lynxpoint_iobp_registers); break; diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 9e98809..716b85c 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -766,6 +766,11 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_C9_MOBILE: + case PCI_DEVICE_ID_INTEL_C9_DESKTOP: + case PCI_DEVICE_ID_INTEL_HM97: + case PCI_DEVICE_ID_INTEL_Z97: + case PCI_DEVICE_ID_INTEL_H97: pmbase = pci_read_word(sb, 0x40) & 0xff80; pm_registers = pch_pm_registers; pm_registers_size = ARRAY_SIZE(pch_pm_registers); diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index bdafa1e..eee6899 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -101,6 +101,11 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_C9_MOBILE: + case PCI_DEVICE_ID_INTEL_C9_DESKTOP: + case PCI_DEVICE_ID_INTEL_HM97: + case PCI_DEVICE_ID_INTEL_Z97: + case PCI_DEVICE_ID_INTEL_H97: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index 1bb5ba2..3cf6051 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -177,6 +177,11 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_C9_MOBILE: + case PCI_DEVICE_ID_INTEL_C9_DESKTOP: + case PCI_DEVICE_ID_INTEL_HM97: + case PCI_DEVICE_ID_INTEL_Z97: + case PCI_DEVICE_ID_INTEL_H97: case PCI_DEVICE_ID_INTEL_H110: case PCI_DEVICE_ID_INTEL_H170: case PCI_DEVICE_ID_INTEL_Z170: @@ -331,6 +336,11 @@ case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: + case PCI_DEVICE_ID_INTEL_C9_MOBILE: + case PCI_DEVICE_ID_INTEL_C9_DESKTOP: + case PCI_DEVICE_ID_INTEL_HM97: + case PCI_DEVICE_ID_INTEL_Z97: + case PCI_DEVICE_ID_INTEL_H97: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: -- To view, visit https://review.coreboot.org/c/coreboot/+/68185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b Gerrit-Change-Number: 68185 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine
by Karthik Ramasubramanian (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68184 to look at the new patch set (#2). Change subject: soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine ...................................................................... soc/amd/common/psp_verstage: Pass SRAM buffer to Crypto Engine Crypto engine prefers the buffer from SRAM. CBFS verification may pass the mapped address of a CBFS file from SPI flash. This causes PSP crypto engine to return invalid address. Hence if the buffer is from SRAM, pass it directly to crypto engine. Else copy into a temporary buffer before passing it to crypto engine. BUG=b:b:227809919 TEST=Build and boot to OS in skyrim with CBFS verification enabled using both x86 verstage and PSP verstage. Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/psp_verstage/vboot_crypto.c 1 file changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68184/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711 Gerrit-Change-Number: 68184 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Update build rules for PSP BIOS image
by Karthik Ramasubramanian (Code Review) 06 Oct '22

06 Oct '22

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68136 ) Change subject: soc/amd/mendocino: Update build rules for PSP BIOS image ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4 Gerrit-Change-Number: 68136 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 06 Oct 2022 22:25:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Reserve more space for metadata
by Karthik Ramasubramanian (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66944 ) Change subject: soc/amd/mendocino: Reserve more space for metadata ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/66944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b7346e2150835443425179048415f3b27d89d89 Gerrit-Change-Number: 66944 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 Oct 2022 22:25:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Add first BIOS block in coreboot.pre
by Karthik Ramasubramanian (Code Review) 06 Oct '22

06 Oct '22

Attention is currently required from: Raul Rangel, Martin L Roth, Julius Werner. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66943 ) Change subject: Add first BIOS block in coreboot.pre ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/66943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209 Gerrit-Change-Number: 66943 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 06 Oct 2022 22:25:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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