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Change subject: mb/google/rex: Enable PD Sync
......................................................................
mb/google/rex: Enable PD Sync
This patch enables PD Sync for Rex.
BUG=b:248775521
TEST=Able to boot Google/Rex with PD sync enabled.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3
---
M src/mainboard/google/rex/Kconfig
1 file changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/67819/3
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68214 )
Change subject: soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68214/comment/f9b3a276_7cbbd568
PS2, Line 9: Function 'setbits16' clears the data register first
> setbits16 actually performs an 'OR' operation with the new data and the origin register entry. […]
Done
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Change subject: soc/amd/morgana: Add initial commit for new SoC
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68195/comment/63dcda92_7f1a207b
PS2, Line 12: commonization.
Did you add TODOs for every file or did you check already which files
might need to be changed?
To keep track of the compatibility of common code, it would be nice to
also add TODOs for the respective Kconfig selects, like it was done in
CB:61077.
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Change subject: mb/google/dedede/var/beadrix: Update SoC gpio pin of USB camera
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register
......................................................................
soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register
Function 'setbits16' performs an 'OR' operation with the new data and
the origin register entry. This can lead to an incorrect value in the
register which can then lead to issues.
Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/elkhartlake/tsn_gbe.c
1 file changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/68214/3
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Change subject: util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
......................................................................
Patch Set 6: Code-Review+2
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Change subject: mb/prodrive/atlas: Print HSID
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/mainboard/prodrive/atlas/gpio.c:
https://review.coreboot.org/c/coreboot/+/68224/comment/da851fe3_a13c2dae
PS1, Line 10: PAD_CFG_GPI(GPP_A8, NONE, RSMRST), /* HSID_0 */
> I just saw they were already configured in early gpios... […]
Ah, probably because *a certain someone* told Sheng to do so 😄
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