coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[S] Change in coreboot[master]: mb/prodrive/atlas: Print HSID
by Maximilian Brune (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Christian Walter, Angel Pons, Lean Sheng Tan. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68224 ) Change subject: mb/prodrive/atlas: Print HSID ...................................................................... Patch Set 2: (4 comments) File src/mainboard/prodrive/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/68224/comment/bc80f367_876618e9 PS1, Line 10: PAD_CFG_GPI(GPP_A8, NONE, RSMRST), /* HSID_0 */ > We should probably configure the GPIOs early in bootblock, as in the future we might need to read th […] I just saw they were already configured in early gpios... Therefore removed them from ramstage gpio table. Weirdly File src/mainboard/prodrive/atlas/mainboard.c: https://review.coreboot.org/c/coreboot/+/68224/comment/0c42ce4f_3dd54096 PS1, Line 11: static void print_hsid(void) > We probably want to have a `uint8_t get_hsid()` function instead, in case we need to deal with revis […] Done https://review.coreboot.org/c/coreboot/+/68224/comment/93b9e77a_fab427e2 PS1, Line 14: < > This is not a shift! 😄 […] Done https://review.coreboot.org/c/coreboot/+/68224/comment/691558de_2202fdfb PS1, Line 17: 1 > No need to restrict the print width, it may actually make bugs harder to diagnose. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b Gerrit-Change-Number: 68224 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 10 Oct 2022 09:03:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register
by Werner Zeh (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Mario Scheithauer, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68214 ) Change subject: soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68214/comment/7b3f12bb_822a8f03 PS2, Line 9: Function 'setbits16' clears the data register first setbits16 actually performs an 'OR' operation with the new data and the origin register entry. This now can lead to a reserved value in the register which can then lead to issues. So please just correct the commit and this CL is fine to go in. -- To view, visit https://review.coreboot.org/c/coreboot/+/68214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915 Gerrit-Change-Number: 68214 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 10 Oct 2022 09:02:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Print HSID
by Maximilian Brune (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Christian Walter, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68224 to look at the new patch set (#2). Change subject: mb/prodrive/atlas: Print HSID ...................................................................... mb/prodrive/atlas: Print HSID Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b --- M src/mainboard/prodrive/atlas/mainboard.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/68224/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b Gerrit-Change-Number: 68224 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Add/Remove LTR disqualification
by Subrata Banik (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Haribalaraman Ramasubramanian, Rizwan Qureshi, Meera Ravindranath, Divagar Mohandass. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 ) Change subject: soc/intel/alderlake: Add/Remove LTR disqualification ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68251/comment/a5da70bf_e7460a61 PS1, Line 7: Add/Remove LTR disqualification for UFS? https://review.coreboot.org/c/coreboot/+/68251/comment/a63b45f6_d919f9b5 PS1, Line 8: : a) Add LTR disqualification in D3 to ensure PMC ignores LTR : from UFS IP as it is infinite. : b) Remove LTR disqualification in _PS0 to ensure PMC stops : ignoring LTR from UFS IP during D3 exit. reading this recommendation reminds me about some W/A or bug fixes due to UFS sku? if yes, can I get the doc details ? Do you have any BUG and TEST case to explain if this code works in proper ? File src/soc/intel/alderlake/acpi/ufs.asl: https://review.coreboot.org/c/coreboot/+/68251/comment/504391ca_f6550d59 PS1, Line 73: 0xFE000000 include iomap.h above and replace hardcoded value with `PCH_PWRM_BASE_ADDRESS` https://review.coreboot.org/c/coreboot/+/68251/comment/850b57e2_99d344df PS1, Line 73: 0x1E30 offset 0x1e30 is not available in external EDS https://review.coreboot.org/c/coreboot/+/68251/comment/80be64d5_ba15afad PS1, Line 78: // Bit 18, IGN_UFSX2 use /* */ Also, can you please add line to explain what is Bit 18 refers to ? https://review.coreboot.org/c/coreboot/+/68251/comment/fc2da6f5_5b97b8f8 PS1, Line 91: 0 can u please use a macro `TRUE` and `FALSE` to represent the `0` and `1` then pass those macros accordingly. ULTR method name is also not clear. may be need one liner to explain -- To view, visit https://review.coreboot.org/c/coreboot/+/68251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c Gerrit-Change-Number: 68251 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Daniil Lunev <dlunev(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Comment-Date: Mon, 10 Oct 2022 08:33:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Docs/architecture: Fix filename for coreboot architecture diagram
by 9elements QA (Code Review) 10 Oct '22

10 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67782 ) Change subject: Docs/architecture: Fix filename for coreboot architecture diagram ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/127018 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/127017 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/127016 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/127015 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/127014 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/127013 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/127012 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/127011 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/127010 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/127009 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/127008 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/127007 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/127006 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/127005 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/127004 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/127003 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/67782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I512646e9af312ba2e1db8f597f6fffa8d54a3515 Gerrit-Change-Number: 67782 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 10 Oct 2022 08:26:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#113) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearPciHeader.c A payloads/cbui/NuklearUI/NuklearPciHeader.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwClock.c A payloads/cbui/NuklearUI/NuklearRwClock.h A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwE820.c A payloads/cbui/NuklearUI/NuklearRwE820.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.c A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.h A payloads/cbui/NuklearUI/NuklearRwSmbios.c A payloads/cbui/NuklearUI/NuklearRwSmbios.h A payloads/cbui/NuklearUI/NuklearRwSmbus.c A payloads/cbui/NuklearUI/NuklearRwSmbus.h A payloads/cbui/NuklearUI/NuklearRwSmram.c A payloads/cbui/NuklearUI/NuklearRwSmram.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearRwUsb.c A payloads/cbui/NuklearUI/NuklearRwUsb.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 128 files changed, 15,958 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/113 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 113 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Add initial fw config
by Subrata Banik (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68220 ) Change subject: mb/google/rex: Add initial fw config ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/rex/variants/rex0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68220/comment/7420e556_94574b6f PS3, Line 156: probe DB_USB USB3 : probe DB_USB USB4 > It will remove unnecessary ACPI code when USB DB is not present on a SKU. Is there any down side of it? i assume those USB DBs are fixed and not configurable so that someone can build a board without those DBs attached. hence, IMO, these are fixed configuration. -- To view, visit https://review.coreboot.org/c/coreboot/+/68220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340 Gerrit-Change-Number: 68220 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 10 Oct 2022 08:17:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable PD Sync
by Kapil Porwal (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67819 ) Change subject: mb/google/rex: Enable PD Sync ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Verified on Google/Rex. -- To view, visit https://review.coreboot.org/c/coreboot/+/67819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3 Gerrit-Change-Number: 67819 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 10 Oct 2022 08:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [TEST ONLY] FSP Build - Debug
by V Sowmya (Code Review) 10 Oct '22

10 Oct '22

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68253 ) Change subject: [TEST ONLY] FSP Build - Debug ...................................................................... [TEST ONLY] FSP Build - Debug Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Ifd57ad5e192b98cc65a07eb2847f3adff8923480 --- M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/alderlake/Kconfig 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/68253/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index f5641ac..8414f8d 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -87,7 +87,7 @@ ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG) - python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" + python 3rdparty/blobs/mainboard/google/nissa/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a73657e..d0d9897 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_ALDERLAKE bool + select HAVE_INTEL_FSP_REPO help Intel Alderlake support. Mainboards should specify the PCH type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead @@ -376,7 +377,7 @@ config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N + default "3rdparty/blobs/mainboard/google/nissa/fsp/AlderLakeFspBinPkg/Client-N/Include" if HAVE_INTEL_FSP_REPO default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT @@ -391,6 +392,7 @@ default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S + default "3rdparty/blobs/mainboard/google/nissa/fsp/AlderLakeFspBinPkg/Client-N/Fsp_debug.fd" if HAVE_INTEL_FSP_REPO config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT int "Debug Consent for ADL" -- To view, visit https://review.coreboot.org/c/coreboot/+/68253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd57ad5e192b98cc65a07eb2847f3adff8923480 Gerrit-Change-Number: 68253 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [TEST ONLY] FSP Build - Release
by V Sowmya (Code Review) 10 Oct '22

10 Oct '22

Attention is currently required from: Tim Wawrzynczak, Andrey Petrov. Hello Tim Wawrzynczak, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67120 to look at the new patch set (#6). Change subject: [TEST ONLY] FSP Build - Release ...................................................................... [TEST ONLY] FSP Build - Release Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Iaad966225e5ac119c8bf4e0112152820dfa31035 --- M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/alderlake/Kconfig 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/67120/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/67120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaad966225e5ac119c8bf4e0112152820dfa31035 Gerrit-Change-Number: 67120 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: Sowmya V <v.sowmya(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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