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I'd like you to reexamine a change. Please visit
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Change subject: mb/prodrive/atlas: Disable C-States & cTDP
......................................................................
mb/prodrive/atlas: Disable C-States & cTDP
As Atlas is targeted for industrial use cases:
- Disable Configurable TDP
- Disable all C-states other than C0/C1 for CPU and package
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: Iaf1c15ac258c78025420966bf592795b66101d17
---
M src/mainboard/prodrive/atlas/Kconfig
M src/mainboard/prodrive/atlas/mainboard.c
2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/68222/2
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Change subject: soc/amd/common: Remove buildtime error for unknown cpu
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/amd/common/block/psp/psp_efs.c:
https://review.coreboot.org/c/coreboot/+/68245/comment/2a22c37f_b47d7c12
PS2, Line 28: #ifndef SPI_MODE_FIELD
Could this be checked in C code?
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Change subject: soc/intel/ehl: Support maximum memory frequency selection
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68097/comment/5db885b7_95f71b50
PS3, Line 9: allwed
allowed
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Change subject: soc/amd/common: Remove buildtime error for unknown cpu
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/ehl: Support maximum memory frequency selection
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Hi Chris, can you fix the Jenkins error?
Sure.. working on it.
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Change subject: soc/intel/ehl: Support maximum memory frequency selection
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Patch Set 3: Verified-1
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-160110):
https://review.coreboot.org/c/coreboot/+/68097/comment/a6b8de57_f7e6230e
PS3, Line 13: - Define maximum memory frequency in mainboard devicetree.cb
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Change subject: soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA register
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68214/comment/81e3613c_7d85c15d
PS3, Line 12:
> In what specification is it documented, how to write the register?
It is described in Mule Creek Canyon EDS Volume 2 Book 2 of 4. Should I still put the reference in the commit message?
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Change subject: payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68255/comment/fa0f277d_35c27cfc
PS3, Line 7: {payloads,src}: Get rid of ALIGN(x, a)
> Maybe: […]
Ack
Patchset:
PS5:
Thx
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Hello build bot (Jenkins), Jeff Daly, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Matt DeVillier, Paul Menzel, Julius Werner, Arthur Heymans, Jason Glenesk, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Fred Reitberger, Felix Held, Tim Chu,
I'd like you to reexamine a change. Please visit
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Change subject: payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
......................................................................
payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84
---
M payloads/coreinfo/cbfs_module.c
M src/lib/bootmem.c
M src/lib/gcov-glue.c
M src/lib/malloc.c
M src/lib/rmodule.c
M src/mainboard/emulation/qemu-i440fx/fw_cfg.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/amd/cezanne/agesa_acpi.c
M src/soc/amd/mendocino/agesa_acpi.c
M src/soc/amd/picasso/agesa_acpi.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/intel/common/mma.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/quark/memmap.c
M src/soc/intel/xeon_sp/nb_acpi.c
M src/soc/intel/xeon_sp/ras/hest.c
M src/soc/samsung/exynos5250/fb.c
20 files changed, 60 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/68255/5
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ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68118 )
Change subject: util/amdfwutil: Order enum and use hex consistently
......................................................................
Patch Set 1: Code-Review+1
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