coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: ec/google/chromec: Expand EC share memory for DTTS
by EricKY Cheng (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Tim Van Patten, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68077 to look at the new patch set (#17). Change subject: ec/google/chromec: Expand EC share memory for DTTS ...................................................................... ec/google/chromec: Expand EC share memory for DTTS DTTS is Dynamic Thermal Table Switching Proposal. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68077/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/68077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Gerrit-Change-Number: 68077 Gerrit-PatchSet: 17 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache
by Arthur Heymans (Code Review) 24 Oct '22

24 Oct '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68641 ) Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Thanks for the info, I always thought it was purely a performance optimisation. Just for my own understanding, how does it work as a security feature since there are other things which are not added to the stage cache, e.g. romstage and FSP-M since they're XIP? > I got confused myself. Using stage cache is indeed a performance optimisation, but in order for that to be secure it has to reside in TSEG. So not using stage cache has no security implications. > > Also https://review.coreboot.org/c/coreboot/+/36674/22 does set up caching for the stage cache region (and cbmem). Maybe that will provide you some performance boosts? > > I did try this out previously, see my comments here: https://review.coreboot.org/c/coreboot/+/67669/comments/3a97af53_86f5fe91 . The problem is that CLFLUSHing cbmem and stage cache at the end of romstage adds ~12 ms, mostly because the FSP reserved memory is so large (5M out of ~5.3M total cbmem size). So we waste time running CLFLUSH on it, even though it should be clean because I don't think coreboot writes to FSP reserved memory. I guess we could find a way to solve this, e.g. provide a way to skip flushing certain cbmem entries, but that might get messy. > I think it's not a bad idea to attempt skipping it as indeed FSP puts things in memory and not coreboot. > Another option is to just select NO_STAGE_CACHE for nissa and other recent Intel Chrome OS devices, as Furquan suggested in b:192032803. Although we technically support S3, we only use S0ix on user devices. So we don't care about optimising S3 resume time, and I assume we're not using the stage cache as a security feature since we have vboot. Let me know if anyone sees an issue with doing this, otherwise I'll upload a CL. That also makes sense. -- To view, visit https://review.coreboot.org/c/coreboot/+/68641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1 Gerrit-Change-Number: 68641 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 10:40:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Expand EC share memory for DTTS
by EricKY Cheng (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Raul Rangel, Ian Feng, Jason Nien, EricKY Cheng, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jason Nien, Isaac Lee, Jon Murphy, Tim Wawrzynczak, Martin Roth, Tim Van Patten, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68077 to look at the new patch set (#16). Change subject: mb/google/skyrim/var/winterhold: Expand EC share memory for DTTS ...................................................................... mb/google/skyrim/var/winterhold: Expand EC share memory for DTTS DTTS is Dynamic Thermal Table Switching Proposal. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/68077/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/68077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Gerrit-Change-Number: 68077 Gerrit-PatchSet: 16 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_apl2: Enable early POST through NC_FPGA
by Uwe Poeche (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Mario Scheithauer, Werner Zeh, Jan Samek. Uwe Poeche has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68743 ) Change subject: mb/siemens/mc_apl2: Enable early POST through NC_FPGA ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a Gerrit-Change-Number: 68743 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 10:06:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
by Subrata Banik (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: David Wu, YH Lin, Ofer Fried, Ren Kuo, Tim Wawrzynczak, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68626 ) Change subject: mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Let Nick to take the call -- To view, visit https://review.coreboot.org/c/coreboot/+/68626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Gerrit-Change-Number: 68626 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ofer Fried <oferfried(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Ofer Fried <oferfried(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 10:02:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
by Shuming Chu (Shuming) (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Angel Pons, Arthur Heymans, Tim Chu. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68567 ) Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm ...................................................................... Patch Set 5: (2 comments) File src/soc/intel/xeon_sp/smihandler.c: https://review.coreboot.org/c/coreboot/+/68567/comment/a668c49b_3a4b3c59 PS4, Line 32: if (CONFIG(DEBUG_SMI)) > This should also depend on `DRIVERS_UART_8250IO`: […] Done. Thanks. https://review.coreboot.org/c/coreboot/+/68567/comment/1d49b454_761d460a PS4, Line 49: if (CONFIG(DEBUG_SMI)) > This should also depend on `DRIVERS_UART_8250IO`: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Gerrit-Change-Number: 68567 Gerrit-PatchSet: 5 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 09:32:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/drivers/uart: Add definition of FIFO enabled in IIR
by Shuming Chu (Shuming) (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Arthur Heymans, Johnny Lin, Christian Walter, Angel Pons, Tim Chu. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68566 ) Change subject: src/drivers/uart: Add definition of FIFO enabled in IIR ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68566/comment/dd4518e3_a31cc670 PS2, Line 7: Interrupt : Identification Register > nit: abbreviate to IIR, as the info is in the commit message body. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 Gerrit-Change-Number: 68566 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 24 Oct 2022 09:15:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
by Shuming Chu (Shuming) (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans, Tim Chu. Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68567 to look at the new patch set (#5). Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm ...................................................................... soc/intel/xeon_sp: Add functions to store/restore uart state in smm When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware initialization that may interfere with OS. Here we store the state before console initialization and restore state before SMM exit. Tested=On not public yet system, after exiting smm, uart console can still work well. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 --- M src/soc/intel/xeon_sp/smihandler.c 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/68567/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Gerrit-Change-Number: 68567 Gerrit-PatchSet: 5 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: src/drivers/uart: Add definition of FIFO enabled in IIR
by Shuming Chu (Shuming) (Code Review) 24 Oct '22

24 Oct '22

Attention is currently required from: Arthur Heymans, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Tim Chu. Hello Arthur Heymans, build bot (Jenkins), Jonathan Zhang, Johnny Lin, Christian Walter, Angel Pons, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68566 to look at the new patch set (#3). Change subject: src/drivers/uart: Add definition of FIFO enabled in IIR ...................................................................... src/drivers/uart: Add definition of FIFO enabled in IIR Interrupt Identification Register (IIR) is a I/O read-access register. Add definition of FIFO enabled for this register so that we can check whether FIFO is enabled or not. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 --- M src/drivers/uart/uart8250reg.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/68566/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 Gerrit-Change-Number: 68566 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo
by Michał Żygowski (Code Review) 24 Oct '22

24 Oct '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68710 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo ...................................................................... util/superiotool/nuvoton.c: fix NCT6687D PP LDN typo Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the patch adding register definitions for NCT6687D Super I/O chip. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/superiotool/nuvoton.c 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index 66dcfce..ea11393 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -90,7 +90,7 @@ {0xff,0xff,0x00,0x00,0x00,0x00,0x10,0x00,0x00, 0x00,0xd5,0x92,0x00,0x80,0x67,0x01,0x00,0x3e, 0x00,0x03,0x0f,0x00,0x00,0x00,MISC,EOT}}, - {0x02, "Parallel Port", + {0x01, "Parallel Port", {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x3f,EOT}}, {0x02, "UART A", -- To view, visit https://review.coreboot.org/c/coreboot/+/68710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca Gerrit-Change-Number: 68710 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2022